PIC16LF1906-E/MV Microchip Technology, PIC16LF1906-E/MV Datasheet - Page 82

• Manufacturer Part Number: PIC16LF1906-E/MV
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 UQFN 4x4x0.5mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16LF1904/6/7
9.1
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1ms. See
Section 22.0 “Electrical Specifications”
LFINTOSC tolerances.
9.2
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word 1. See
9.2.1
When the WDTE bits of Configuration Word 1 are set to
‘11’, the WDT is always on.
WDT protection is active during Sleep.
9.2.2
When the WDTE bits of Configuration Word 1 are set to
‘10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
9.2.3
When the WDTE bits of Configuration Word 1 are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See
for more details.
TABLE 9-1:
TABLE 9-2:
DS41569A-page 82
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Change INTOSC divider (IRCF bits)
WDTE<1:0>
Independent Clock Source
WDT Operating Modes
11
10
01
00
WDT IS ALWAYS ON
WDT IS OFF IN SLEEP
WDT CONTROLLED BY SOFTWARE
Table
WDT OPERATING MODES
WDT CLEARING CONDITIONS
9-1.
SWDTEN
X
X
1
0
X
Conditions
Device
Awake
Mode
Sleep
X
X
X
Disabled
Disabled
Disabled
Table 9-1
Active
Active
Active
Mode
for the
WDT
Preliminary
9.3
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.
9.4
The WDT is cleared when any of the following condi-
tions occur:
• Any Reset
• CLRWDT instruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fail event
• WDT is disabled
• Oscillator Start-up TImer (OST) is running
See
9.5
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See
Module”
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See
STATUS register
Table 9-2
Time-Out Period
Clearing the WDT
Operation During Sleep
for more information on the OST.
Section 3.0 “Memory Organization”
for more information.
(Register
Cleared until the end of OST
 2011 Microchip Technology Inc.
3-1) for more information.
Section 6.0 “Oscillator
Unaffected
Cleared
WDT
and