PIC16LF1906-E/MV Microchip Technology, PIC16LF1906-E/MV Datasheet - Page 232

• Manufacturer Part Number: PIC16LF1906-E/MV
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 UQFN 4x4x0.5mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16LF1904/6/7
MOVIW
Syntax:
Operands:
Operation:
Status Affected:
Description:
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41569A-page 232
Mode
Preincrement
Predecrement
Postincrement
Postdecrement
Move literal to BSR
[ label ] MOVLB k
0  k  15
k  BSR
None
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
Move INDFn to W
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
n  [ 0 , 1 ]
mm  [ 00 , 01 , 10 , 11 ]
-32  k  31
INDFn  W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
--FSRn
Z
Syntax
++FSRn
FSRn++
FSRn--
mm
00
01
10
11
Preliminary
MOVLP
Syntax:
Operands:
Operation:
Status Affected:
Description:
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
Words:
Cycles:
Example:
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Words:
Cycles:
Example:
Move literal to W
[ label ]
0  k  255
k  (W)
None
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assem-
ble as ‘ 0 ’s.
1
1
After Instruction
Move literal to PCLATH
[ label ] MOVLP k
0  k  127
k  PCLATH
None
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
Move W to f
[ label ]
0  f  127
(W)  (f)
None
Move data from W register to register
‘f’.
1
1
Before Instruction
After Instruction
MOVLW
MOVWF
 2011 Microchip Technology Inc.
OPTION_REG = 0xFF
OPTION_REG = 0x4F
MOVLW k
W
MOVWF
0x5A
OPTION_REG
=
0x5A
W = 0x4F
W = 0x4F
f