PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 229

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PIC18LF27J13T-I/SO

Manufacturer Part Number
PIC18LF27J13T-I/SO
Description
28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18LF27J13T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FIGURE 15-5:
15.5.5
When Timer3/5 gate value status is utilized, it is
possible to read the most current level of the gate con-
trol value. The value is stored in the TxGVAL bit
(TxGCON<2>). The TxGVAL bit is valid even when the
Timer3/5 gate is not enabled (TMRxGE bit is cleared).
 2010 Microchip Technology Inc.
TMRxGIF
TMRxGE
TxGSPM
TxDONE
TxGPOL
Timer3/5
TxGGO/
TxGVAL
TxG_IN
TxGTM
TxCKI
TIMER3/5 GATE VALUE STATUS
TIMER3/5 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
Cleared by Software
N
Counting Enabled on
Rising Edge of TxG
Set by Software
Preliminary
N + 1
PIC18F47J13 FAMILY
Falling Edge of TxGVAL
N + 2
15.5.6
When the Timer3/5 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer3/5 gate is not enabled (TMRxGE bit is cleared).
Set by Hardware on
N + 3
TIMER3/5 GATE EVENT
INTERRUPT
Cleared by Hardware on
Falling Edge of TxGVAL
N + 4
DS39974A-page 229
Cleared by
Software

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