PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 546

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F47J13 FAMILY
Extended Instruction Set
External Clock Input ........................................................... 38
F
Fail-Safe Clock Monitor ............................................ 415, 428
Fast Register Stack (FSR) ................................................. 85
Firmware Instructions ....................................................... 433
Flash Program Memory
Flash Program Memory .................................................... 107
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 454
H
Hardware Multiplier .......................................................... 117
High/Low-Voltage Detect ................................................. 391
I
I/O Ports ........................................................................... 139
DS39974A-page 546
ADDFSR .................................................................. 476
ADDULNK ................................................................ 476
CALLW ..................................................................... 477
MOVSF .................................................................... 477
MOVSS .................................................................... 478
PUSHL ..................................................................... 478
SUBFSR ................................................................... 479
SUBULNK ................................................................ 479
Interrupts in Power-Managed Modes ....................... 430
POR or Wake-up From Sleep .................................. 430
WDT During Oscillator Failure ................................. 429
Write Sequence ........................................................ 115
Associated Registers ............................................... 116
Control Registers ..................................................... 108
Erase Sequence ....................................................... 112
Erasing ..................................................................... 112
Operation During Code-Protect ................................ 116
Reading .................................................................... 111
Table Pointer
Table Pointer Boundaries ......................................... 110
Table Reads and Table Writes ................................. 107
Write Sequence ........................................................ 113
Writing ...................................................................... 113
8 x 8 Multiplication Algorithms .................................. 117
Operation ................................................................. 117
Performance Comparison (table) ............................. 117
Applications .............................................................. 395
Associated Registers ............................................... 396
Characteristics ......................................................... 505
Current Consumption ............................................... 393
Effects of a Reset ..................................................... 396
Operation ................................................................. 392
Setup ........................................................................ 393
Start-up Time ........................................................... 393
Typical Application ................................................... 395
Open-Drain Outputs ................................................. 140
Pin Capabilities ........................................................ 139
TTL Input Buffer Option ............................................ 140
EECON1 and EECON2 ................................... 108
TABLAT (Table Latch) Register ....................... 110
TBLPTR (Table Pointer) Register .................... 110
Boundaries Based on Operation ...................... 110
Unexpected Termination .................................. 116
Write Verify ...................................................... 116
During Sleep .................................................... 396
Preliminary
I
I
INCF ................................................................................ 454
INCFSZ ............................................................................ 455
In-Circuit Debugger .......................................................... 431
In-Circuit Serial Programming (ICSP) .......................415, 431
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 480
Indirect Addressing .......................................................... 102
INFSNZ ............................................................................ 455
Initialization Conditions for All Registers .......................71–79
Instruction Cycle ................................................................ 86
Instruction Set .................................................................. 433
2
2
C Mode .......................................................................... 310
C Mode (MSSP)
Acknowledge Sequence Timing .............................. 338
Associated Registers ............................................... 344
Baud Rate Generator ............................................... 331
Bus Collision
Clock Arbitration ...................................................... 333
Clock Stretching ....................................................... 325
Clock Synchronization and CKP bit ......................... 326
Effects of a Reset .................................................... 339
General Call Address Support ................................. 329
I
Master Mode ............................................................ 329
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 339
Operation ................................................................. 315
Read/Write Bit Information (R/W Bit) ................315, 318
Registers .................................................................. 310
Serial Clock (SCLx Pin) ........................................... 318
Slave Mode .............................................................. 315
Sleep Operation ....................................................... 339
Stop Condition Timing ............................................. 338
and Standard PIC18 Instructions ............................. 480
Clocking Scheme ....................................................... 86
Flow/Pipelining ........................................................... 86
ADDLW .................................................................... 439
ADDWF .................................................................... 439
ADDWF (Indexed Literal Offset Mode) .................... 481
ADDWFC ................................................................. 440
ANDLW .................................................................... 440
ANDWF .................................................................... 441
BC ............................................................................ 441
BCF .......................................................................... 442
BN ............................................................................ 442
BNC ......................................................................... 443
BNN ......................................................................... 443
2
C Clock Rate w/BRG ............................................. 332
During a Repeated Start Condition .................. 342
During a Stop Condition ................................... 343
10-Bit Slave Receive Mode (SEN = 1) ............ 325
10-Bit Slave Transmit Mode ............................ 325
7-Bit Slave Receive Mode (SEN = 1) .............. 325
7-Bit Slave Transmit Mode .............................. 325
Operation ......................................................... 331
Reception ........................................................ 335
Repeated Start Condition Timing ..................... 334
Start Condition Timing ..................................... 333
Transmission ................................................... 335
and Arbitration ................................................. 339
Addressing ....................................................... 315
Addressing Masking Modes
Reception ........................................................ 318
Transmission ................................................... 318
5-Bit ......................................................... 316
7-Bit ......................................................... 317
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