PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 287

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 19-5:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
CMPL1
R/W-0
The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2> = 11 and
PxM<1:0> = 00.
CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits
1 = Modulated output pin toggles between PxA and PxB for each period
0 = Complementary output assignment is disabled; the STRD:STRA bits are used to determine Steer-
Unimplemented: Read as ‘0’
STRSYNC: Steering Sync bit
1 = Output steering update occurs on the next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
STRD: Steering Enable D bit
1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxD pin is assigned to a port pin
STRC: Steering Enable C bit
1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxC pin is assigned to a port pin
STRB: Steering Enable B bit
1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxB pin is assigned to a port pin
STRA: Steering Enable A bit
1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxA pin is assigned to a port pin
CMPL0
R/W-0
ing mode
PSTRxCON: PULSE STEERING CONTROL
(1, ACCESS FBFh; 2, FB9h; 3, BANKED F1Ah)
W = Writable bit
‘1’ = Bit is set
U-0
—
STRSYNC
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F47J13 FAMILY
R/W-0
STRD
(1)
R/W-0
STRC
x = Bit is unknown
R/W-0
STRB
DS39974A-page 287
R/W-1
STRA
bit 0