PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 169

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

REGISTER 16-2:
© 2011-2012 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14-13 Unimplemented: Read as ‘0’
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-5
bit 3
bit 2
bit 1-0
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
2:
SPISGNEXT
SPISGNEXT: Sign Extend Read Data from the RX FIFO bit
1 = Data from RX FIFO is sign extended
0 = Data from RX FIFO is not sign extened
FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame Error overflow generates error events
0 = Frame Error does not generate error events
SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = Receive overflow generates error events
0 = Receive overflow does not generate error events
SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun Generates Error Events
0 = Transmit Underrun Does Not Generates Error Events
IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)
1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data
0 = A ROV is a critical error which stop SPI operation
IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)
1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error which stop SPI operation
AUDEN: Enable Audio CODEC Support bit
1 = Audio protocol enabled
0 = Audio protocol disabled
Unimplemented: Read as ‘0’
AUDMONO: Transmit Audio Data Format bit
1 = Audio data is mono (Each data word is transmitted on both left and right channels)
0 = Audio data is stereo
Unimplemented: Read as ‘0’
AUDMOD<1:0>: Audio Protocol Mode bit
11 = PCM/DSP mode
10 = Right Justified mode
01 = Left Justified mode
00 = I
This bit can only be written when the ON bit = 0.
This bit is only valid for AUDEN = 1.
31/23/15/7
AUDEN
R/W-0
R/W-0
Bit
U-0
U-0
—
—
2
S mode
(1)
SPIxCON2: SPI CONTROL REGISTER 2
30/22/14/6
Bit
U-0
U-0
U-0
U-0
—
—
—
—
W = Writable bit
‘1’ = Bit is set
29/21/13/5
Bit
U-0
U-0
U-0
U-0
—
—
—
—
Preliminary
FRMERREN
28/20/12/4
(1,2)
(1)
R/W-0
(1,2)
Bit
U-0
U-0
U-0
—
—
—
AUDMONO
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SPIROVEN
27/19/11/3
R/W-0
R/W-0
Bit
U-0
U-0
—
—
PIC32MX1XX/2XX
(1,2)
SPITUREN IGNROV
26/18/10/2
R/W-0
Bit
U-0
U-0
U-0
—
—
—
x = Bit is unknown
25/17/9/1
AUDMOD<1:0>
R/W-0
R/W-0
DS61168D-page 169
Bit
U-0
U-0
—
—
24/16/8/0
IGNTUR
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(1,2)