PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 212

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 22-1:
DS61168D-page 212
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12-9
bit 8
bit 7-6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
Range
31:24
23:16
15:8
7:0
Bit
2:
ON: Comparator ON bit
1 = Module is enabled. Setting this bit does not affect the other bits in this register
0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this
COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin
0 = Comparator output is not driven on the output CxOUT pin
CPOL: Comparator Output Inversion bit
1 = Output is inverted
0 = Output is not inverted
Unimplemented: Read as ‘0’
COUT: Comparator Output bit
1 = Output of the Comparator is a ‘1’
0 = Output of the Comparator is a ‘0’
EVPOL<1:0>: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled
Unimplemented: Read as ‘0’
CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CV
0 = Comparator non-inverting input is connected to the C
Unimplemented: Read as ‘0’
CCH<1:0>: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IV
10 = Comparator inverting input is connected to the CxIND pin
01 = Comparator inverting input is connected to the CxINC pin
00 = Comparator inverting input is connected to the CxINB pin
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.
31/23/15/7
ON
R/W-0
R/W-1
register
Bit
U-0
U-0
—
—
EVPOL<1:0>
(1)
CMXCON: COMPARATOR CONTROL REGISTER
30/22/14/6
R/W-0
COE
R/W-1
Bit
U-0
U-0
—
—
(1)
W = Writable bit
‘1’ = Bit is set
29/21/13/5
CPOL
R/W-0
Bit
U-0
U-0
U-0
—
—
—
(2)
Preliminary
(2)
28/20/12/4
CREF
R/W-0
Bit
U-0
U-0
U-0
—
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
REF
X
Bit
U-0
U-0
U-0
U-0
—
—
—
—
INA pin
REF
26/18/10/2
© 2011-2012 Microchip Technology Inc.
Bit
U-0
U-0
U-0
U-0
—
—
—
—
x = Bit is unknown
25/17/9/1
R/W-1
Bit
U-0
U-0
U-0
—
—
—
CCH<1:0>
24/16/8/0
COUT
R/W-1
Bit
U-0
U-0
R-0
—
—