PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 205

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

REGISTER 21-1:
© 2011-2012 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8
bit 7-5
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
2:
3:
ON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC module is not operating
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
FORM<2:0>: Data Output Format bits
011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)
010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)
001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)
000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)
110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)
101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)
100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = CTMU ends sampling and starts conversion
010 = Timer 3 period match ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing SAMP bit ends sampling and starts conversion
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC
bit is automatically cleared by hardware to end sampling and start conversion.
This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
31/23/15/7
ON
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(1)
AD1CON1: ADC CONTROL REGISTER 1
SSRC<2:0>
30/22/14/6
R/W-0
Bit
U-0
U-0
U-0
—
—
—
W = Writable bit
‘1’ = Bit is set
29/21/13/5
(1)
R/W-0
SIDL
R/W-0
Bit
U-0
U-0
—
—
Preliminary
28/20/12/4
CLRASAM
R/W-0
Bit
U-0
U-0
U-0
—
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
Bit
U-0
U-0
U-0
U-0
—
—
—
—
PIC32MX1XX/2XX
26/18/10/2
ASAM
R/W-0
R/W-0
Bit
U-0
U-0
—
—
FORM<2:0>
x = Bit is unknown
R/W-0, HSC
25/17/9/1
SAMP
R/W-0
Bit
U-0
U-0
—
—
DS61168D-page 205
(2)
24/16/8/0
R/C-0, HSC
DONE
≠
R/W-0
‘0’, this
Bit
U-0
U-0
—
—
(3)