PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 218

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

REGISTER 24-1:
DS61168D-page 218
Legend:
R = Readable bit
-n = Value at POR
bit 31
bit 30
bit 29-26 EDG1SEL<3:0>: Edge 1 Source Select bits
bit 25
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
2:
3:
4:
EDG1MOD: Edge1 Edge Sampling Select bit
1 = Input is edge-sensitive
0 = Input is level-sensitive
EDG1POL: Edge 1 Polarity Select bit
1 = Edge1 programmed for a positive edge response
0 = Edge1 programmed for a negative edge response
1111 = C3OUT pin is selected
1110 = C2OUT pin is selected
1101 = C1OUT pin is selected
1100 = IC3 Capture Event is selected
1011 = IC2 Capture Event is selected
1010 = IC1 Capture Event is selected
1001 = CTED8 pin is selected
1000 = CTED7 pin is selected
0111 = CTED6 pin is selected
0110 = CTED5 pin is selected
0101 = CTED4 pin is selected
0100 = CTED3 pin is selected
0011 = CTED1 pin is selected
0010 = CTED2 pin is selected
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
EDG2STAT: Edge2 Status bit
Indicates the status of Edge2 and can be written to control edge source
1 = Edge2 has occurred
0 = Edge2 has not occurred
EDG1MOD EDG1POL
EDG2MOD EDG2POL
31/23/15/7
When this bit is set for Pulse Delay Generation, the EDG2SEL<2:0> bits must be set to ‘1110’ to select
C2OUT.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications
Characteristics”
This bit setting is not available for the CTMU temperature diode.
R/W-0
R/W-0
R/W-0
R/W-0
ON
Bit
CTMUCON: CTMU CONTROL REGISTER
30/22/14/6
R/W-0
R/W-0
R/W-0
U-0
Bit
—
for current values.
W = Writable bit
‘1’ = Bit is set
CTMUSIDL
29/21/13/5
R/W-0
R/W-0
R/W-0
R/W-0
Bit
ITRIM<5:0>
Preliminary
28/20/12/4
TGEN
R/W-0
R/W-0
R/W-0
R/W-0
Bit
EDG1SEL<3:0>
EDG2SEL<3:0>
(1)
(Table
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
EDGEN
R/W-0
R/W-0
R/W-0
R/W-0
Bit
29-39) in
EDGSEQEN IDISSEN
26/18/10/2
Section 29.0 “Electrical
R/W-0
R/W-0
R/W-0
R/W-0
Bit
© 2011-2012 Microchip Technology Inc.
x = Bit is unknown
EDG2STAT EDG1STAT
25/17/9/1
R/W-0
R/W-0
R/W-0
U-0
Bit
—
IRNG<1:0>
(2)
24/16/8/0
CTTRIG
R/W-0
R/W-0
R/W-0
Bit
U-0
—