S29AS008J70BFI030 Spansion Inc., S29AS008J70BFI030 Datasheet

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S29AS008J70BFI030

Manufacturer Part Number
S29AS008J70BFI030
Description
IC 8M FLASH MEMORY
Manufacturer
Spansion Inc.
Datasheet

Specifications of S29AS008J70BFI030

Cell Type
NOR
Density
8Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Bottom/Top
Address Bus
20/19Bit
Operating Supply Voltage (typ)
1.8V
Operating Temp Range
-40C to 85C
Package Type
FBGA
Program/erase Volt (typ)
1.65 to 1.95V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.65V
Operating Supply Voltage (max)
1.95V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
12mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Compliant
S29AS008J
8 Megabit (1M x 8-Bit / 512K x 16-Bit)
CMOS 1.8 Volt-only Boot Sector Flash Memory
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Publication Number S29AS008J_00
Notice On Data Sheet Designations
Revision 08
Issue Date July 16, 2009
for definitions.
S29AS008J Cover Sheet

Related parts for S29AS008J70BFI030

S29AS008J70BFI030 Summary of contents

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S29AS008J 8 Megabit (1M x 8-Bit / 512K x 16-Bit) CMOS 1.8 Volt-only Boot Sector Flash Memory Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may ...

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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...

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... Publication Number S29AS008J_00 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com- binations offered may occur ...

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General Description The S29AS008J Mbit, 1.8 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words with a x8/x16 bus and either top or bottom boot sector architecture. The device is offered in 48-pin TSOP and 48- ...

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Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Figures Figure 7.1 In-System Sector Group Protect/Unprotect Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 7.2 Temporary ...

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Tables Table 7.1 S29AS008J Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Product Selector Guide Speed Option Max access time ACC Max CE# access time Max OE# access time Note See AC Characteristics on page 43 2. Block Diagram RY/BY RESET# ...

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Connection Diagrams 3.1 Standard TSOP A15 1 2 A14 A13 3 A12 4 A11 5 6 A10 WE# 11 RESET WP# 14 RY/BY# 15 A18 16 A17 17 ...

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FBGA Connection Diagram A6 A13 WE# A3 RY/BY 3.3 Special Handling Instructions Special handling is required for Flash Memory products in BGA packages. Flash memory devices in BGA packages may be damaged ...

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Pin Configuration A0–A18 DQ0–DQ14 DQ15/A-1 BYTE# CE# OE# WE# WP# RESET# RY/BY Logic Symbol addresses 15 data inputs/outputs DQ15 (data input/output, word ...

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Ordering Information 6.1 S29AS008J Standard Products Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29AS008J 70 Valid Combinations Valid Combinations list configurations ...

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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of ...

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Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE For program operations, the BYTE# pin determines whether ...

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RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to V progress, tristates all data output pins, and ignores all read/write attempts ...

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Table 7.2 S29AS008J Autoselect Codes (High Voltage Method) Description CE# OE# WE# Manufacturer ID Spansion Cycle Cycle Device ID Cycle Sector Group Protection L L ...

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Sector A18 A17 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 0 SA6 0 0 SA7 0 0 SA8 0 0 SA9 0 0 SA10 0 0 SA11 0 1 SA12 ...

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Sector Group Protection/Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group (see Table 7.3 on page 17 re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection ...

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Figure 7.1 In-System Sector Group Protect/Unprotect Algorithms START PLSCNT = 1 RESET Wait 1 μs No First Write Temporary Sector Cycle = 60h? Group Unprotect Mode Yes Set up sector address Sector Group Protect: Write 60h to sector ...

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Temporary Sector Group Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to V protected sectors can be programmed or erased by ...

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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system ...

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Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon Sector Indicator Bit ...

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The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area, and none of the bits in the Secured Silicon Sector memory space can be modified ...

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Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, ...

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Addresses Addresses (Word Mode) (Byte Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Table 9.3 ...

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Addresses Addresses (Word Mode) (Byte Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h July 16, 2009 S29AS008J_00_08 Table 9.4 Primary Vendor-Specific ...

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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 11.1 on page 33 address and data values or writing them in the improper sequence resets the device to reading array ...

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Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the ...

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Note See Table 11.1 on page 33 10.7 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock ...

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Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the ...

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The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. ...

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Command Definitions Table 11.1 S29AS008J Command Definitions (Word Mode) Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 XXX Manufacturer ID 4 Device ID, 6 Top Boot Block Device ID, 6 Bottom Boot Block Secured ...

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Table 11.2 S29AS008J Command Definitions (Byte Mode) Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Manufacturer ID 4 Device ID, 6 Top Boot Block Device ID, 6 Bottom Boot Block Secured Silicon Sector Factory 4 Protect, ...

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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 12.1 on page 39 RY/BY#, and DQ6 each offer a method for determining whether a ...

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Notes Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...

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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at ...

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Reading Toggle Bits DQ6/DQ2 Refer to Figure 12.2 on page 38 toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store ...

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DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle ...

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Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground V (Note 1) CC A9, RESET# (Note 2) All other pins (Note 1) Output Short Circuit Current Notes 1. Minimum DC voltage ...

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DC Characteristics 15.1 CMOS Compatible Parameter I Input Load Current LI WP# Input Load Current I LI A9, RESET# Input Load Current I Output Leakage Current LO V Active Read Current CC I CC1 (Note 1) V Active Write ...

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Test Conditions Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 17. Key to Switching Waveforms Waveform Vcc Input 0 ...

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AC Characteristics 18.1 Read Operations Parameter JEDEC Std t t AVAV AVQV ACC t t ELQV GLQV EHQZ GHQZ DF t OEH t t AXQX OH Notes ...

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Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms READY Read or Write RESET# Pin Low (NOT During Embedded Algorithms READY Read or Write t RESET# Pulse Width RP t RESET# High ...

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Word/Byte Configuration (BYTE#) Parameter JEDEC Std t ELFL/ t FLQZ t FHQV CE# OE# BYTE# BYTE# DQ0–DQ14 Switching from word to byte mode DQ15/A-1 BYTE# BYTE# Switching DQ0–DQ14 from byte to word mode DQ15/A-1 CE# WE# BYTE# Note Refer ...

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Erase/Program Operations Parameter JEDEC Std t t AVAV AVWL WLAX DVWH WHDX DH t OES t t GHWL GHWL t t ELWL WHEH CH ...

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Addresses CE# OE# WE# Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data (see 2. Illustration shows device in word mode. Addresses CE OE# ...

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Addresses CE# OE# WE# DQ6/DQ2 RY/BY# Note VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 18.9 DQ2 vs. DQ6 for Erase ...

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Temporary Sector Group Unprotect Parameter JEDEC Std t VIDR t RSP Note Not 100% tested RESET 1.95 V CE# WE# RY/BY RESET# SA, A6, A1, A0 Data CE# WE# OE# Note ...

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Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std t t AVAV AVEL ELAX DVEH EHDX DH t OES t t GHEL GHEL t t WLEL WS t ...

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Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time (Note 3) Notes 1. Typical program and erase times assume the following conditions Under worst case conditions ...

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Physical Dimensions 21.1 TS 048 - 48-Pin Standard TSOP STANDARD PIN OUT (TOP VIEW SEE DETAIL 0.25 2X (N/2 TIPS) PARALLEL TO SEATING PLANE Jedec MO-142 (D) DD Symbol MIN NOM A A1 ...

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VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8. 6.15 mm INDEX MARK PIN A1 CORNER PACKAGE VBK 048 JEDEC 8. 6.15 mm NOM PACKAGE SYMBOL MIN NOM A --- A1 0.18 A2 0.62 ...

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Revision History Section Revision 01 (July 27, 2007) Initial release. Revision 02 (October 30, 2007) Ordering Information Deleted all Leaded package offerings Table Primary Vendor-Specific Corrected the data of CFI address 44 Hex Extended Query Revision 03 (June 6, ...

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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2007-2009 Spansion Inc. All rights reserved. Spansion EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. ...

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