S29AS008J70BFI030 Spansion Inc., S29AS008J70BFI030 Datasheet - Page 29

• Manufacturer Part Number: S29AS008J70BFI030
• Description: IC 8M FLASH MEMORY
• Manufacturer: Spansion Inc.

Specifications of S29AS008J70BFI030

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom/Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: FBGA
• Program/erase Volt (typ): 1.65 to 1.95V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.65V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

10.4
10.5
10.6
July 16, 2009 S29AS008J_00_08
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command
Sequence
Word/Byte Program Command Sequence
Unlock Bypass Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic
serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle
Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit
Secured Silicon Sector command sequence returns the device to normal operation.
addresses and data requirements for both command sequences. Note that the unlock bypass mode is not
available when the device enters the Secured Silicon Sector. For further information, see
Sector Flash Memory Region on page
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming
is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles,
followed by the program set-up command. The program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not required to provide further controls or timings.
The device automatically generates the program pulses and verifies the programmed cell margin.
on page 33
When the Embedded Program algorithm is complete, the device then returns to reading array data and
addresses are no longer latched. The system can determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The Byte Program command sequence
should be reinitiated once the device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from
a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling
algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still
0. Only erase operations can convert a 0 to a 1.
The unlock bypass feature allows the system to program bytes or words to the device faster than using the
standard program command sequence. The unlock bypass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time.
requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. The first cycle must contain the data 90h; the second cycle the data F0h. Addresses are don’t care
for both cycles. The device then returns to reading array data.
Figure 10.1 on page 30
on page 46
shows the address and data requirements for the byte program command sequence.
for parameters, and to
illustrates the algorithm for the program operation. See
D a t a
Write Operation Status on page 35
Figure 18.5 on page 46
S h e e t
23.
S29AS008J
for timing diagrams.
for information on these status bits.
Table 11.1 on page 33
Erase/Program Operations
Table 11.1
shows the
Secured Silicon
shows the
Table 11.1
29