ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet - Page 23

• Manufacturer Part Number: ISP1504A1ETTM
• Manufacturer: STEricsson

Specifications of ISP1504A1ETTM

• Lead Free Status / RoHS Status: Compliant

CD00222688
Product data sheet
Fig 6.
DATA[7:0]
REG1V8
V
PWRDN
internal
CLOCK
CC(I/O)
CS_N/
XTAL1
POR
V
NXT
STP
DIR
CC
t1 = V
t2 = V
HIGH.
t3 = CS_N/PWRDN is asserted.
t4 = The ISP1504x1 regulator starts to turn on. UPLI pads are not in 3-state and may drive to either LOW or HIGH. It is
recommended that the link ignores ULPI pins status during t
t5 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined level.
DIR is driven to HIGH and the other pins are driven to LOW.
t6 = The 19.2 MHz or 26 MHz input clock starts. This clock may be started any time.
t7 = The internal PLL is stabilized after t
be stabilized after t
The link is expected to issue a RESET command to initialize the ISP1504x1.
t8 = The power-up sequence is completed and the ULPI bus interface is ready for use.
Power-up and reset sequence required before the ULPI bus is ready for use
t1
CC
CC(I/O)
t2
is applied to the ISP1504x1.
is turned on. ULPI interface pins (CLOCK, DATA[7:0], DIR and NXT) are in 3-state as long as CS_N/PWRDN is
t3
t
REGUP
startup(PLL)
t4
t
POR
from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW.
t5 t6
startup(PLL)
t
startup(PLL)
Rev. 04 — 20 May 2010
. If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will
t7
internal clocks stable
REGUP
RESET command
TXCMD
+ t
ISP1504A1; ISP1504C1
POR
D
.
internal reset
ULPI HS USB OTG transceiver
© ST-ERICSSON 2010. All rights reserved.
RXCMD
update
004aaa768
bus idle
t8
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