ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet - Page 37

• Manufacturer Part Number: ISP1504A1ETTM
• Manufacturer: STEricsson

Specifications of ISP1504A1ETTM

• Lead Free Status / RoHS Status: Compliant

CD00222688
Product data sheet
9.10.1 Full-speed or low-speed host-initiated suspend and resume
9.10 USB suspend and resume
ISP1504x1 operates just as in full-speed mode, and sends all data with full-speed rise and
fall times. Whenever the link transmits a USB packet in preamble mode, the ISP1504x1
will automatically send a preamble header at full-speed bit rate before sending the link
packet at low-speed bit rate. The ISP1504x1 will ensure a minimum gap of four full-speed
bit times between the last bit of the full-speed PRE PID and the first bit of the low-speed
packet SYNC. The ISP1504x1 will drive a J for at least one full-speed bit time after
sending the PRE PID, after which the pull-up resistor can hold the J state on the bus. An
example transmit packet is shown in
In preamble mode, the ISP1504x1 can also receive low-speed packets from the full-speed
bus.
Figure 17
suspend and sometime later initiates resume signaling to wake up the downstream
peripheral. Note that
LINESTATE updates.
The sequence of events for a host and a peripheral, both with ISP1504x1, is as follows:
1. Idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down
2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend
Fig 16. Preamble sequence
DATA[7:0]
resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 Ω
terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 kΩ
pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is
set to 1b).
state. The peripheral link places the PHY into low-power mode by setting the
SUSPENDM bit in the Function Control register, causing the PHY to draw only
suspend current. The host may or may not be powered down.
DP or DM
CLOCK
NXT
STP
DIR
DP and DM timing is not to scale.
illustrates how a host or a hub places a full-speed or low-speed peripheral into
Figure 17
FS SYNC
Rev. 04 — 20 May 2010
TXCMD (low-speed packet ID)
timing is not to scale, and does not show all RXCMD
PRE ID
FS
Figure
IDLE (min
4 FS bits)
ISP1504A1; ISP1504C1
16.
LS SYNC
D0
ULPI HS USB OTG transceiver
LS PID
D1
LS D0
© ST-ERICSSON 2010. All rights reserved.
LS D1
004aaa714
37 of 78