ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet - Page 55

• Manufacturer Part Number: ISP1504A1ETTM
• Manufacturer: STEricsson

Specifications of ISP1504A1ETTM

• Lead Free Status / RoHS Status: Compliant

Table 39.
Table 40.
Table 41.
Legend: * reset value
Table 42.
CD00222688
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Bit
Symbol
Reset
Access
Symbol
-
LINESTATE1
LINESTATE0
Symbol
SCRATCH[7:0]
Debug register (address R = 15h) bit allocation
Debug register (address R = 15h) bit description
Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
10.1.10 Scratch register
10.1.12 Access extended register set
10.1.13 Vendor-specific registers
10.1.14 Power Control register
10.1.11 Reserved
10.1.9 Debug register
R/W/S/C
R
7
0
7
0
The bit allocation of the Debug register is given in
current value of signals useful for debugging.
This is an empty register for testing purposes, see
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Address 30h to 3Fh contains vendor-specific registers.
This register controls various aspects of the ISP1504x1.
of the register.
Description
reserved
Line State 1: Contains the current value of LINESTATE 1
Line State 0: Contains the current value of LINESTATE 0
Access
R/W/S/C
R/W/S/C
R
6
0
6
0
reserved
Value
00h*
R/W/S/C
R
5
0
5
0
Description
Scratch: This is an empty register byte for testing purposes. Software can
read, write, set and clear this register, and the functionality of the PHY will
not be affected.
reserved
Rev. 04 — 20 May 2010
R/W/S/C
R
4
0
4
0
ISP1504A1; ISP1504C1
BVALID_
R/W/S/C
FALL
R
3
0
3
0
Table
Table
BVALID_
R/W/S/C
RISE
39. This register indicates the
Table 42
41.
ULPI HS USB OTG transceiver
R
2
0
2
0
shows the bit allocation
R/W/S/C
STATE1
© ST-ERICSSON 2010. All rights reserved.
LINE
R
1
0
1
0
reserved
R/W/S/C
STATE0
LINE
R
0
0
0
0
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