ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet - Page 36

• Manufacturer Part Number: ISP1504A1ETTM
• Manufacturer: STEricsson

Specifications of ISP1504A1ETTM

• Lead Free Status / RoHS Status: Compliant

CD00222688
Product data sheet
Fig 14. High-speed transmit-to-transmit packet timing
Fig 15. High-speed receive-to-transmit packet timing
CLOCK
CLOCK
DATA
DP or
DATA
DP or
DIR
[7:0]
NXT
STP
DM
[7:0]
STP
NXT
DIR
DM
D
D
N−1
N−4
DATA
D
D
N
N−3
9.9 Preamble
D
EOP
N−2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the
DATA
(three to eight clocks)
TX end delay (two to five clocks)
D
RX end delay
N−1
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
EOP
Rev. 04 — 20 May 2010
link decision time (1 to 14 clocks)
link decision time (15 to 24 clocks)
USB interpacket delay (88 to 192 high-speed bit times)
IDLE
ISP1504A1; ISP1504C1
IDLE
ULPI HS USB OTG transceiver
© ST-ERICSSON 2010. All rights reserved.
(one to two clocks)
(one to two clocks)
TXCMD
TX start delay
TXCMD
TX start delay
SYNC
D0
004aaa713
SYNC
004aaa712
D0
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D1
D1