ISP1507D1HNUM STEricsson, ISP1507D1HNUM Datasheet - Page 13

• Manufacturer Part Number: ISP1507D1HNUM
• Manufacturer: STEricsson

Specifications of ISP1507D1HNUM

• Lead Free Status / RoHS Status: Compliant

9. Modes of operation
CD00269906
Product data sheet
9.1.1 Synchronous mode
9.1 ULPI modes
The ISP1507D1 ULPI bus can be programmed to operate in four modes. Each mode
reconfigures the signals on the data bus as described in the following subsections. Setting
more than one mode will lead to undefined behavior.
This is default mode. At power-up, and when CLOCK is stable, the ISP1507D1 will enter
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
synchronous mode is given in
This mode is used by the link to perform the following tasks:
For more information on various synchronous mode protocols, see
Table 4.
Signal
name
CLOCK
DATA[7:0] I/O
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
ULPI signal description
Direction on
ISP1507D1
O
[1]
Rev. 03 — 28 July 2010
Signal description
60 MHz interface clock. If a crystal is attached or a clock is driven
into the XTAL1 pin, the ISP1507D1 will drive a 60 MHz output clock.
8-bit data bus. In synchronous mode, the link drives DATA[7:0] to
LOW by default. The link initiates transfers by sending a nonzero
data pattern called TXCMD (transmit command). In synchronous
mode, the direction of DATA[7:0] is controlled by DIR. Contents of
DATA[7:0] lines must be ignored for exactly one clock cycle
whenever DIR changes value. This is called the turnaround cycle.
Data lines have fixed direction and different meaning in low-power
and serial modes.
Table
Section
4.
ULPI HS USB host and peripheral transceiver
16. A description of the ULPI pin behavior in
ISP1507D1
Section
© ST-ERICSSON 2010. All rights reserved.
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