ISP1507D1HNUM STEricsson, ISP1507D1HNUM Datasheet - Page 50

• Manufacturer Part Number: ISP1507D1HNUM
• Manufacturer: STEricsson

Specifications of ISP1507D1HNUM

• Lead Free Status / RoHS Status: Compliant

Table 34.
Table 35.
Table 36.
Table 37.
CD00269906
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1
0
Symbol
-
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit description
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description
Symbol
-
SESS_END
SESS_VALID
VBUS_VALID
HOST_DISCON
11.1.7 USB_INTR_STAT register
11.1.8 USB_INTR_L register
R
R
X
7
7
0
This register (see
The bits of the USB_INTR_L register are automatically set by the ISP1507D1 when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1507D1
will automatically clear all bits when the link reads this register, or when the ISP1507D1
enters low-power or serial mode.
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in
X
R
R
6
6
0
Description
reserved
Session end latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
Session valid latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host disconnect latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
BUS
Description
reserved
Session end: Reflects the current value of the session end voltage comparator.
Session valid: Reflects the current value of the session valid voltage comparator.
V
Host disconnect: Reflects the current value of the host disconnect detector.
reserved
reserved
BUS
valid latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
valid: Reflects the current value of the V
Table
R
R
5
X
5
0
Rev. 03 — 28 July 2010
34) indicates the current value of the interrupt source signal.
R
R
4
0
4
0
ULPI HS USB host and peripheral transceiver
SESS_
SESS_
END_L
Table
END
R
R
3
0
3
0
36.
BUS
VALID_L
SESS_
SESS_
VALID
valid voltage comparator.
R
R
2
0
2
0
ISP1507D1
VALID_L
VBUS_
VBUS_
VALID
© ST-ERICSSON 2010. All rights reserved.
R
R
1
0
1
0
DISCON_L
DISCON
HOST_
HOST_
R
R
0
0
0
0
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