ISP1507D1HNUM STEricsson, ISP1507D1HNUM Datasheet - Page 51

• Manufacturer Part Number: ISP1507D1HNUM
• Manufacturer: STEricsson

Specifications of ISP1507D1HNUM

• Lead Free Status / RoHS Status: Compliant

Table 38.
Table 39.
Table 40.
Legend: * reset value
Table 41.
CD00269906
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Bit
Symbol
Reset
Access
Symbol
SCRATCH
[7:0]
DEBUG - Debug register (address R = 15h) bit allocation
DEBUG - Debug register (address R = 15h) bit description
SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
11.1.10 SCRATCH register
11.1.12 Access extended register set
11.1.13 Vendor-specific registers
11.1.14 PWR_CTRL register
11.1.11 Reserved
11.1.9 DEBUG register
R/W/S/C
Symbol
-
LINESTATE1
LINESTATE0
R
7
0
7
0
The bit allocation of the DEBUG register is given in
current value of signals useful for debugging.
Table 40
testing purposes.
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the ISP1507D1.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Addresses 30h to 3Fh contain vendor-specific registers.
Table 41
Access
R/W/S/C
R/W/S/C
R
6
0
6
0
shows the bit description of the SCRATCH register. It is an empty register for
provides the bit allocation of the PWR_CTRL register.
reserved
Value
00h*
Description
reserved
Line state 1: Contains the current value of LINESTATE 1
Line state 0: Contains the current value of LINESTATE 0
R/W/S/C
R
5
0
5
0
reserved
Description
Scratch: This is an empty register byte for testing purposes. Software
can read, write, set, and clear this register. The functionality of the
ISP1507D1 will not be affected.
Rev. 03 — 28 July 2010
R/W/S/C
R
4
0
4
0
ULPI HS USB host and peripheral transceiver
BVALID_
R/W/S/C
FALL
R
3
0
3
0
Table
BVALID_
R/W/S/C
RISE
R
38. This register indicates the
2
0
2
0
ISP1507D1
reserved
R/W/S/C
STATE1
© ST-ERICSSON 2010. All rights reserved.
LINE
R
1
0
1
0
IGNORE_
R/W/S/C
STATE0
RESET
LINE
R
0
0
0
0
51 of 73