ISP1507D1HNUM STEricsson, ISP1507D1HNUM Datasheet - Page 32

• Manufacturer Part Number: ISP1507D1HNUM
• Manufacturer: STEricsson

Specifications of ISP1507D1HNUM

• Lead Free Status / RoHS Status: Compliant

CD00269906
Product data sheet
Fig 11. High-speed transmit-to-transmit packet timing
Fig 12. High-speed receive-to-transmit packet timing
CLOCK
CLOCK
DATA
DP or
DATA
DP or
DIR
[7:0]
NXT
STP
DM
[7:0]
STP
NXT
DIR
DM
D
D
N−1
N−4
DATA
D
10.9 Preamble
D
N
N−3
D
EOP
N−2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the FUNC_CTRL register (see
DATA
(three to eight clocks)
TX end delay (two to five clocks)
D
RX end delay
N−1
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
EOP
Rev. 03 — 28 July 2010
link decision time (1 to 14 clocks)
link decision time (15 to 24 clocks)
USB interpacket delay (88 to 192 high-speed bit times)
IDLE
ULPI HS USB host and peripheral transceiver
IDLE
Section
ISP1507D1
© ST-ERICSSON 2010. All rights reserved.
11.1.2). When in
(one to two clocks)
(one to two clocks)
TXCMD
TX start delay
TXCMD
TX start delay
SYNC
D0
004aaa713
SYNC
004aaa712
D0
32 of 73
D1
D1