SAF7118EHV1 NXP Semiconductors, SAF7118EHV1 Datasheet
SAF7118EHV1
Specifications of SAF7118EHV1
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SAF7118EHV1 Summary of contents
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SAF7118 Multistandard video decoder with adaptive comb filter and component video input Rev. 04 — 4 July 2008 1. General description The SAF7118 is a video capture device that, due to its improved comb filter performance, is suitable for various ...
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... NXP Semiconductors The circuit is I rate up to 400 kbit/s). 2. Features 2.1 Video acquisition/clock sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. VSB signals eight analog inputs, split as desired four analog component inputs, with embedded or separate sync, split as desired I Four on-chip anti-aliasing fi ...
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... NXP Semiconductors 2.4 Video scaler I Horizontal and vertical downscaling and upscaling to randomly sized windows I Horizontal and vertical scaling range: variable zoom to that the H and V zoom are restricted by the transfer data rates) I Anti-alias and accumulating filter for horizontal scaling I Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing ...
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... NXP Semiconductors I Software controlled power saving standby modes supported I Programming via serial 400 kbit/s I Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994” Applications I General industrial video applications I In-car TV reception I In-car entertainment I In-car navigation platforms 4. Quick reference data Table 1 ...
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ADP[8:0] RES CLKEXT CE DNC0 to DNC20 CONTROL EXMCLR AD PORT FSW AI11 FAST SWITCH DELAY ANALOG1 AI12 and R AI13 ADC1 G AI14 COMPONENTS PROCESSING AI1D B RAW AI21 ANALOG2 AI22 and AI23 C CHROMINANCE ADC2 AI24 PROCESSING AI2D ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning 1 SAF7118H 40 Fig 2. Pin configuration (QFP160) Table 3. Pin Symbol A2 XTOUT A6 XRDY A10 XPD4 B1 AI41 B5 TDI B9 XPD3 B13 DNC7 C3 DNC9 C7 XRH C11 XPD7 D1 AI43 D5 V SSD13 D9 V SSD11 D13 DNC1 E3 AI31 E13 HPD2 F3 AI33 F13 HPD5 ...
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... NXP Semiconductors Table 3. Pin Symbol H13 IPD4 J3 AI24 J13 IPD6 K3 AI1D K13 IGP1 L3 AI14 L7 ADP3 L11 V M1 AOUT M13 FSW N3 DNC15 N7 ADP5 N11 ASCLK P2 DNC18 P6 ADP8 P10 SDA 7.2 Pin description Table 4. Pin description Symbol Pin QFP160 HBGA156 DNC6 1 B2 AI41 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin QFP160 HBGA156 AI34 18 G1 AI21 SSA2 AI22 21 G3 AI2D 22 H1 AI23 DDA2 DDA2A AI24 26 J3 AI11 SSA1 AI12 29 K1 AI1D 30 K3 AI13 DDA1 DDA1A AI14 34 L3 AGNDA 35 L2 AOUT DDA0 SSA0 DNC13 39 N1 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin QFP160 HBGA156 ADP4 57 P7 ADP3 DDD3 ADP2 60 M7 ADP1 61 P8 ADP0 SSD3 INT_A DDD4 SCL SSD4 SDA 68 P10 RTS0 69 M10 RTS1 70 N10 RTCO 71 L10 AMCLK 72 P11 V 73 M11 DDD5 ASCLK 74 N11 ALRCLK 75 P12 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin QFP160 HBGA156 IGP0 87 L14 V 88 L11 SSD5 IGP1 89 K13 IGPV 90 K14 IGPH 91 K12 IPD7 92 K11 IPD6 93 J13 IPD5 94 J14 V 95 J12 DDD6 V 96 J11 SSD6 IPD4 97 H13 IPD3 98 H14 IPD2 99 H11 IPD1 100 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin QFP160 HBGA156 DNC7 117 B13 DNC8 118 B14 DNC11 119 C12 DNC12 120 C13 DNC21 121 - DNC22 122 - DNC3 123 A13 DNC4 124 B12 DNC5 125 A12 XTRI 126 B11 XPD7 127 C11 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin QFP160 HBGA156 TDI 152 B5 V 153 D5 SSD13 V 154 A4 SS(xtal) XTALI 155 B4 XTALO 156 A3 V 157 B3 DD(xtal) XTOUT 158 A2 DNC9 159 C3 DNC10 160 C4 [ input output power not connected strapping pull-up pull-down open-drain. [2] Pin strapping is done by connecting the pin to the supply via a 3.3 k resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level ...
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Table 5. 8-bit/16-bit and alternative pin function configurations [1] Pin Symbol Input 8-bit input 16-bit input modes modes (only for I programming) C11, A11, B10, XPD7 to D1 data Y data input A10, B9, A9, B8, A8 XPD0 input (127, ...
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Table 5. 8-bit/16-bit and alternative pin function configurations [1] Pin Symbol Input 8-bit input 16-bit input modes modes (only for I programming) N12 (77) ITRDY - - K12 (91) IGPH - - K14 (90) IGPV - - K13 (89) IGP1 ...
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... NXP Semiconductors 8. Functional description 8.1 Decoder 8.1.1 Analog input processing The SAF7118 offers sixteen analog signal inputs, four analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC with a Decimation Filter (DF); see The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit ...
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... NXP Semiconductors AI44 AI43 SOURCE CLAMP AI42 SWITCH CIRCUIT AI41 AI4D AI34 AI33 SOURCE CLAMP AI32 SWITCH CIRCUIT AI31 AI3D AI24 AI23 SOURCE CLAMP AI22 SWITCH CIRCUIT AI21 AI2D AI14 AI13 CLAMP SOURCE AI12 SWITCH CIRCUIT AI11 AI1D MODE CLAMP CONTROL ...
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... NXP Semiconductors 8.1.1.2 Gain control The gain control circuit receives (via the I amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input COntrol (AICO). The AGC for luminance is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. Component inputs are gain adjusted manually at a fi ...
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... NXP Semiconductors Fig 9. SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 1 NO ACTION VBLK 0 1 > 510 0 1 < > 496 + LLC2 STOP GAIN ACCUMULATOR (18 BITS system variable Y = AGV FGV > GUDL GUDL = gain update level (adjustable) ...
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... NXP Semiconductors Fig 10. Clamp and gain flow chart SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter ANALOG INPUT ADC 1 NO BLANKING ACTIVE VBLK <- CLAMP 1 0 HCL 1 0 CLL NO CLAMP CLAMP CLAMP WIPE = white peak level (510) SBOT = sync bottom level (1) CLL = clamp level [120 for CVBS, Y(C), S ...
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CVBS-IN or Y-IN LDEL COMPENSATION YCOMB QUADRATURE MODULATOR CVBS-IN QUADRATURE LOW-PASS 1 or CHR-IN DEMODULATOR DOWNSAMPLING SUBCARRIER GENERATION 2 CHROMINANCE INCREMENT DELAY SUBCARRIER GENERATION 1 HUEC[7:0] RTCO Fig 11. Chrominance and luminance processing Y DELAY LUMINANCE-PEAKING SUBTRACTOR OR LOW-PASS, CHR ...
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... NXP Semiconductors 8.1.2.1 Chrominance path The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis). The frequency is dependent on the chosen color standard. ...
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... NXP Semiconductors • Loop filter chrominance PLL (only active for PAL/NTSC standards) • PAL/SECAM sequence detection 2-switch generation The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. 51 (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111 Fig 12. Transfer characteristics of the chrominance low-pass at CHBW = 0 SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. 51 (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111 Fig 13. Transfer characteristics of the chrominance low-pass at CHBW = 1 SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter ...
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... NXP Semiconductors 8.1.2.2 Luminance path The rejection of the chrominance components within the 9-bit CVBS or Y input signal is achieved by subtracting the remodulated chrominance signal from the CVBS input. The comb filtered C 3 block. Its characteristic is controlled by LUBW (subaddress 09h, bit D4) to modify the width of the chrominance ‘ ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. ...
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... NXP Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 (dB (5) LCBW[2:0] = 001. 48 (6) LCBW[2:0] = 011. ...
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... NXP Semiconductors 9 V (dB (1) LUFI[3:0] = 0001. 2 (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. 1 (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = 0111. (8) LUFI[3:0] = 0000 (dB (9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. 27 (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. 30 (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. 33 (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111. ...
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... NXP Semiconductors 8.1.2.3 Brightness Contrast Saturation (BCS) control and decoder output levels The resulting Y (CVBS) and C following functions: • Chrominance saturation control by DSAT7 to DSAT0 • Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0 • Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0 • ...
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... NXP Semiconductors a. Sources containing 7.5 IRE black Fig 20. CVBS (raw data) range for scaler input, data slicer and X port output 8.1.3 Synchronization The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop fi ...
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... NXP Semiconductors Table 6. Clock XTALO LLC LLC2 LLC4 (internal) LLC8 (virtual) LFCO Fig 21. Block diagram of the clock generation circuit 8.1.5 Power-on reset and CE input A missing clock, insufficient digital or analog V the reset sequence; all outputs are forced to 3-state (see RES is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system ...
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... NXP Semiconductors CE XTALO LLCINT RESINT LLC RES (internal reset) some ms POC = Power-on control CE = chip enable input XTALO = crystal oscillator output LLCINT = internal system clock RESINT = internal reset LLC = line-locked clock output RES = reset output Fig 22. Power-on control circuit SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors (1) CE raises with digital 3.3 V supply voltage (pulled up to this supply voltage) (2) The order of the supplies has no meaning (3) Optional reset pulse can be applied any time after minimum 5 ms when all supplies are stable Fig 23. CE raises with digital 3.3 V supply voltage (1) CE keeps LOW during power-up (e ...
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... NXP Semiconductors 8.2.1 RGB-to-(Y-C The matrix converts the RGB signals from the analog-to-digital converters/downsamplers to the Y-C has a gain factor of 1. The block provides a delay compensated bypass for component input signals. The matrix is represented by the following equations: • 0.299 • 0.5772 B • ...
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... NXP Semiconductors Fig 27. C Fig 28. Y high-pass filter frequency response 8.2.3 Component video BCS control The resulting Y and C contains the following functions: • Chrominance saturation control by CSAT7 to CSAT0 • Luminance contrast and brightness control by CCON7 to CCON0 and CBRI7 to CBRI0 • Limiting Y-C Recommendation 601/656” ...
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... NXP Semiconductors 255 white 235 128 LUMINANCE 100 % 16 black 0 001aac241 “ITU Recommendation 601/656” digital levels with default CBCS (decoder) settings CCON[7:0] = 44h, CBRI[7:0] = 80h and CSAT[7:0] = 40h. Equations for modification to the Y Int Luminance: OUT C C Chrominance OUT It should be noted that the resulting levels are limited 254 in accordance with “ITU Recommendation 601/656” . ...
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... NXP Semiconductors Table 7. Data type number Data type SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter Data formats at decoder output teletext EuroWST, CCST European closed caption Video Programming Service (VPS) wide screen signalling bits US teletext (WST) US closed caption (line 21) ...
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LINE NUMBER (1st FIELD) active video 259 260 261 LINE NUMBER (2nd FIELD) active video LCR LINE NUMBER (1st FIELD) 273 274 275 276 LINE NUMBER (2nd FIELD) LCR ...
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... NXP Semiconductors ITU counting 622 623 310 single field counting 309 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 134h VGATE FID ITU counting 309 310 single field counting 310 309 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 134h VGATE FID (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the fi ...
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... NXP Semiconductors ITU counting 525 single field counting 262 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 101h VGATE FID ITU counting 263 262 single field counting 262 263 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 101h VGATE FID (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the fi ...
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... NXP Semiconductors Fig 34. Horizontal timing diagram (50/60 Hz) 8.4 Scaler The High Performance video Scaler (HPS) is based on the system as implemented in previous products, but with some aspects enhanced. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers, and handshake. The internal data fl ...
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... NXP Semiconductors The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer. Depending on the actual programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced signifi ...
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... NXP Semiconductors The video scaler receives its input signal from the video decoder or from the expansion port (X port). It gets 16-bit Y-C from the decoder. Discontinuous data stream can be accepted from the expansion port (X port), normally 8-bit wide ITU 656 such as Y-C qualifi ...
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... NXP Semiconductors • Vertical length defined in number of target lines result of vertical scaling, parameter YD[11:0] 9Fh[3:0] 9Eh[7:0] • Horizontal offset defined in number of pixels of the video source, parameter XO[11:0] 95h[3:0] 94h[7:0] • Horizontal length defined in number of pixels of the video source, parameter XS[11:0] 97h[3:0] 96h[7:0] • ...
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... NXP Semiconductors Table 9. XDV1 92h[ 8.4.1.2 Task handling The task handler controls the switching between the two programming register sets controlled by subaddresses 90h and C0h. A task is enabled via the global control bits TEA[80h[4]] and TEB[80h[5]]. The handler is then triggered by events, which can be defined for each register set. ...
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... NXP Semiconductors • Basically the trigger conditions are checked, when a task is activated important to realize, that they are not checked while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[1: YO[11:0] = 310 and task B STRC[1: YO[11:0] = 310 results in output fi ...
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Table 10. Examples for field processing Subject Field sequence frame/field [1] Example 1 Example 2 1/1 1/2 2/1 1/1 Processed by task State of detected ITU 656 FID TOGGLE fl ...
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... NXP Semiconductors 8.4.2 Horizontal scaling The overall horizontal required scaling factor has to be split into a binary and a rational value according to the equation: H-scale ratio H-scale ratio where the parameter of prescaler XPSC[5: and the parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For ...
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... NXP Semiconductors Where: • The range (value 0 is not allowed) • Npix_in = number of input pixel, and • Npix_out = number of desired output pixel over the complete horizontal scaler The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification can be calculated according to the equation: ...
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... NXP Semiconductors Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. Figure 35 Table 11. PFUV[1:0] A2h[7:6] and PFY[1:0] A2h[5: (1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11. Fig 35. Luminance prefilter characteristic (1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11. ...
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... NXP Semiconductors (dB 0. XC2_1 = 0; Zero’s at Fig 37. Examples for prescaler filter characteristics: effect of increasing XACL[5:0] (dB) (1) XC2_1 = 0 and XACL[5: (2) XC2_1 = 1 and XACL[5: (3) XC2_1 = 0 and XACL[5: (4) XC2_1 = 1 and XACL[5: (5) XC2_1 = 0 and XACL[5: (6) XC2_1 = 1 and XACL[5: Fig 38. Examples for prescaler filter characteristics: setting XC2_1 = 1 ...
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... NXP Semiconductors Table 12. XACL[5:0] example of usage Prescale XPSC Recommended values ratio [5:0] For lower bandwidth requirements XACL[5: [1] Resulting FIR function. 8.4.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses A8h to AFh and D8h to DFh) The horizontal fine scaling (VPD) should operate at scaling ratios between (0 ...
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... NXP Semiconductors Luminance and chrominance scale increments (XSCY[12:0] A9h[4:0] A8h[7:0] and XSCC[12:0] ADh[4:0] ACh[7:0]) are defined independently, but must be set relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAh[7:0] and XPHC[7:0] AEh[7:0] can be used to shift the sample phases slightly. ...
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... NXP Semiconductors 8.4.3.2 Vertical scaler (subaddresses B0h to BFh and E0h to EFh) Vertical scaling of any ratio from 64 (theoretical zoom) to The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes; Linear Phase Interpolation (LPI) and accumulation (ACM) mode. These are controlled by YMODE[B4h[0]]: • ...
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... NXP Semiconductors 8.4.3.3 Use of the vertical phase offsets As described in interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H-sync at the falling edge of V-sync may result in different field ID interpretation. A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fi ...
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... NXP Semiconductors Fig 40. Derivation of the phase related equations (example: interlace vertical scaling In Table 13 It should be noted that the equations of the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field; see If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the phase shift (PHO + 16) that can be skipped ...
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... NXP Semiconductors Table 13. Input field under processing Upper input lines Upper input lines Lower input lines Lower input lines Table 14. Detected input field upper lines 0 = upper lines 1 = lower lines 1 = lower lines [1] Case 1: OFIDC[90h[6 scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines ...
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... NXP Semiconductors 8.5 VBI data decoder and capture (subaddresses 40h to 7Fh) The SAF7118 contains a versatile VBI data decoder. The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The result is buffered into a dedicated VBI data FIFO with a capacity of 2 frequency, signal source, fi ...
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... NXP Semiconductors Table 15. DT[3:0] 62h[3:0] 1101 1110 1111 [1] See errata information in 8.6 Image port output formatter (subaddresses 84h to 87h) The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I port and a decoding and multiplexing unit, which generates the 8-bit or 16-bit wide output data stream and the accompanied reference and supporting information ...
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... NXP Semiconductors 8.6.1 Scaler output formatter (subaddresses 93h and C3h) The output formatter organizes the packing into the output FIFO. The following formats are available: Y-C Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93h[2:0], FOI[1:0] 93h[4:3] and FYSK[93h[5]]. The data formats are defined on double words, or multiples, and are similar to the video formats as recommended for PCI multimedia applications (compares to SAA7146A), but planar formats are not supported ...
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... NXP Semiconductors These are: • The FIFO Almost Empty (FAE) flag • The FIFO Combined Flag (FCF) or FIFO filled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark • The FIFO Almost Full (FAF) flag • ...
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... NXP Semiconductors 8.6.5 Data stream coding and reference signal generation (subaddresses 84h, 85h and 93h and V reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates. ...
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VBI line timing reference code ... SAV SDID DC ... EAV ANC header DID SDID DC ANC header active for DID (subaddress 5Dh) ...
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... NXP Semiconductors Table 21. Bytes stream of the data slicer Nick Comment name DID, subaddress 5Dh = 00h SAV, subaddress 5Dh EAV subaddress 5Dh [ 3Eh subaddress 5Dh [ 3Fh SDID programmable via subaddress 5Eh [8] DC IDI1 IDI2 CS check sum byte BC valid byte count [1] NEP = inverted EP; for EP see ...
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... NXP Semiconductors 8.7.1 Master audio clock The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters: • Audio master Clocks Per Field, ACPF[17:0] 32h[1:0] 31h[7:0] 30h[7:0] according to the equation: • ...
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... NXP Semiconductors 8.7.2 Signals ASCLK and ALRCLK Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the following parameters: • SDIV[5:0] 38h[5:0] according to the equation: SDIV[5:0] • ...
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... NXP Semiconductors 9. Input/output interfaces and ports The SAF7118 has 5 different I/O interfaces: • Analog video input interface, for analog CVBS and/or Y and C input signals and/or component video signals • Audio clock port • Digital real-time signal port (RT port) • Digital video expansion port (X port), for unscaled digital video input and output • ...
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... NXP Semiconductors 9.2 Audio clock signals The SAF7118 also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame. ...
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... NXP Semiconductors The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAF7118. The function of the RTS1 and RTS0 pins can be defi ...
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... NXP Semiconductors FIDT: detected field frequency has changed (50 Hz RDCAP: ready for capture (true DCSTD[1:0]: detected color standard has changed or color lost. COPRO, COLSTR and TYPE3: various levels of copy protection have changed. 9.4.1.3 VBI data slicer VPSV: VPS identification found or lost. ...
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... NXP Semiconductors Table 28. Symbol Pin XPD7 to XPD0 XCLK XDQ XRDY XRH XRV XTRI [1] Pin numbers for QFP160 in parenthesis. 9.5.1 X port configured as output If data output is enabled at the expansion port, then the data stream from the decoder is presented. The data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers LCR2 to LCR24 ...
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... NXP Semiconductors – Adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing This data type is defined for future enhancements. It could be activated for lines containing standard test signals within the vertical blanking period. Currently the most sources do not contain test lines. The nominal levels are illustrated in • ...
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... NXP Semiconductors Table 30. Bit Table 31. Line number 261 262 263 264 and 265 266 to 282 283 284 285 to 524 525 SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter SAV/EAV format on expansion port XPD7 to XPD0 Symbol Description logic 1 F field bit 1st fi ...
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... NXP Semiconductors Table 32. Line number 309 310 311 and 312 313 to 335 336 337 to 622 623 624 and 625 9.5.2 X port configured as input If the data input mode is selected at the expansion port, then the scaler can select its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit SCSRC[1:0] 91h[5:4]) ...
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... NXP Semiconductors The data formats at the image port are defined in double words of 32 bits (4 bytes), such as the related FIFO structures. However the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data ...
Page 78
... NXP Semiconductors – Recoded VBI data bytes (8-bit) directly placed in ANC data field, 00h and FFh codes will be recoded to even parity codes 03h and FCh to suppress invalid ITU-R BT.656 codes There are no empty cycles in the ancillary code and its data field. The data codes 00h and FFh are suppressed (changed to 01h or FEh respectively) in the active video stream, as well as in the VBI raw sample stream (VBI pass-through) ...
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... NXP Semiconductors Table 34. Symbol Pin HPD7 to HPD0 [1] Pin numbers for QFP160 in parenthesis. 9.8 Basic input and output timing diagrams I port and X port 9.8.1 I port output timing The following diagrams illustrate the output timing via the I port. IGPH and IGPV are logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the output data qualifi ...
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... NXP Semiconductors ICLK IDQ IPD [ 7:0 ] IGPH Fig 43. Output timing I port for serial 8-bit data at start of a line (ICODE = 0) ICLK IDQ IPD [ 7 IGPH Fig 44. Output timing I port for serial 8-bit data at end of a line (ICODE = 1) ICLK IDQ IPD [ 7 IGPH Fig 45. Output timing I port for serial 8-bit data at end of a line (ICODE = 0) ...
Page 81
... NXP Semiconductors ICLK IDQ IPD [ 7 HPD [ 7 SAV IGPH Fig 46. Output timing for 16-bit data output via I port and H port with codes (ICODE = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle IDQ IGPH IGPV Fig 47. H gate and V gate output timing ...
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... NXP Semiconductors 2 10. I C-bus description The SAF7118 supports the ‘fast mode’ I 400 kbit/s). 2 10.1 I C-bus format S SLAVE ADDRESS W a. Write procedure. S SLAVE ADDRESS W Sr SLAVE ADDRESS R b. Read procedure (combined). 2 Fig 49. I C-bus format 2 Table 35. Description of I C-bus format Code ...
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... NXP Semiconductors Table 36. Subaddress 00h F0h to FFh Video decoder: 01h to 1Fh 01h to 05h 06h to 19h 1Ah to 1Dh 1Eh and 1Fh Component processing and interrupt masking: 20h to 2Fh 20h to 22h 23h to 25h 26h to 28h 29h to 2Ch 2Dh to 2Fh Audio clock generation: 30h to 3Fh ...
Page 84
Table 37. I C-bus receiver/transmitter overview Register function Subaddress Chip version: register 00h Chip version (read only) 00h Video decoder: registers 01h to 1Fh Front-end part: registers 01h to 05h Increment delay 01h Analog input control 1 02h Analog ...
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Table 37. I C-bus receiver/transmitter overview Register function Subaddress Reserved 1Ah to 1Dh Status byte 1 video decoder (read only) 1Eh Status byte 2 video decoder (read only) 1Fh Component processing and interrupt masking part: registers 20h to 2Fh ...
Page 86
Table 37. I C-bus receiver/transmitter overview Register function Subaddress General purpose VBI data slicer part: registers 40h to 7Fh Slicer control 1 40h LCR2 to LCR24 ( 24) 41h to 57h Programmable framing code 58h Horizontal ...
Page 87
Table 37. I C-bus receiver/transmitter overview Register function Subaddress Task A definition: registers 90h to BFh Basic settings and acquisition window definition Task handling control 90h X port formats and configuration 91h X port input reference signal definition 92h ...
Page 88
Table 37. I C-bus receiver/transmitter overview Register function Subaddress Horizontal phase scaling Horizontal luminance scaling increment A8h A9h Horizontal luminance phase offset AAh Reserved ABh Horizontal chrominance scaling ACh increment ADh Horizontal chrominance phase offset AEh Reserved AFh Vertical ...
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Table 37. I C-bus receiver/transmitter overview Register function Subaddress Horizontal input window start C4h C5h Horizontal input window length C6h C7h Vertical input window start C8h C9h Vertical input window length CAh CBh Horizontal output window length CCh CDh ...
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Table 37. I C-bus receiver/transmitter overview Register function Subaddress Vertical scaling Vertical luminance scaling increment E0h E1h Vertical chrominance scaling increment E2h E3h Vertical scaling mode control E4h Reserved E5h to E7h Vertical chrominance phase offset ‘00’ E8h Vertical ...
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... NXP Semiconductors 2 10.2 I C-bus details 10.2.1 Subaddress 00h Table 38. Chip Version (CV) identification; 00h[7:4]; read only register Function Logic levels ID7 Chip Version (CV) CV3 10.2.2 Subaddress 01h The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only. ...
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... NXP Semiconductors 10.2.3 Subaddress 02h Table 40. Analog input control 1 (AICO1); 02h[7:0] Bit Description D[7:6] analog function select; see Figure 4 and Figure 6 CVBS modes 1 D[5:0] mode selection modes 1 D[5:0] mode selection SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter ...
Page 93
... NXP Semiconductors Table 40. Analog input control 1 (AICO1); 02h[7:0] Bit Description CVBS modes 2 D[5:0] mode selection modes 2 D[5:0] mode selection CVBS modes 3 D[5:0] mode selection SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter [1] …continued Symbol Value MODE[5:0] 00 1110 00 1111 ...
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... NXP Semiconductors Table 40. Analog input control 1 (AICO1); 02h[7:0] Bit Description Y-P -P modes B R D[5:0] mode selection RGB modes D[5:0] mode selection SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb filter [1] …continued Symbol Value MODE[5:0] 10 0000 10 0001 10 0010 to 10 1101 ...
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... NXP Semiconductors Table 40. Analog input control 1 (AICO1); 02h[7:0] Bit Description VSB modes; see Figure 90 D[5:0] mode selection [1] Always refer to Table 70, usage of bits FSWE and FSWI. [2] To take full advantage of the Y/C modes and the I (full luminance bandwidth). SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 50. Mode 00 CVBS1 AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 52. Mode 02 CVBS3 SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 54. Mode 04 CVBS5 AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 56. Mode 06 YC1 (gain ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 58. Mode 08 YC1 (gain adapted to AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 60. Mode 0A YC3 (gain ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 62. Mode 0C YC3 (gain adapted to AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 64. Mode 0E CVBS7 ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 66. Mode 10 CVBS9 AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 68. Mode 12 CVBS11 SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 70. Mode 14 CVBS13 AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 72. Mode 16 YC5 (gain ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 74. Mode 18 YC5 (gain adapted to Y AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 76. Mode 1A YC7 (gain ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 78. Mode 1C YC7 (gain adapted to Y AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 80. Mode 1E CVBS15 ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 82. Mode 20 SY-P AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 84. Mode 2E SY-P SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 86. Mode 30 SRGB1 AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 88. Mode 3E SRGB3 SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors Fig 90. VSB modes (use CVBS modes with REFA = 1, DOSL = and GAFIX = 1) 10.2.4 Subaddress 03h Table 41. Analog input control 2 (AICO2); 03h[6:0] Bit Description D6 HL not reference select D5 AGC hold during vertical blanking period D4 color peak off D3 automatic gain control integration D2 gain control fi ...
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... NXP Semiconductors 10.2.5 Subaddress 04h Table 42. Analog input control 3 (AICO3): static gain control channel 1; 03h[0] and 04h[7:0] Decimal Gain (dB) Sign bit value 03h[0] GAI18 0... 3 0 ...144 0 0 145... 0 0 ...511 +6 1 10.2.6 Subaddress 05h Table 43. Analog input control 4 (AICO4); static gain control channel 2; 03h[1] and 05h[7:0] ...
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... NXP Semiconductors 10.2.8 Subaddress 07h Table 45. Horizontal sync stop; 07h[7:0] Delay time (step Control bits size = 8 / LLC) HSS7 128... 109 (50 Hz) forbidden (outside available central counter range) 128... 108 (60 Hz) 108 (50 Hz)... 1 107 (60 Hz)... 1 ...108 (50 Hz) 0 ...107 (60 Hz) 0 109...127 (50 Hz) forbidden (outside available central counter range) 108 ...
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... NXP Semiconductors 10.2.10 Subaddress 09h Table 47. Luminance control; 09h[7:0] Bit Description D7 chrominance trap/comb filter bypass D6 adaptive luminance comb filter D5 processing delay in non comb filter mode D4 remodulation bandwidth for luminance; see Figure 14 to Figure 17 D[3:0] sharpness control, luminance filter characteristic; see Figure 18 10 ...
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... NXP Semiconductors 10.2.12 Subaddress 0Bh Table 49. Luminance contrast control: decoder part; 0Bh[7:0] Gain Control bits DCON7 1.984 (maximum) 0 1.063 (ITU level (luminance off (inverse luminance (inverse luminance) 1 10.2.13 Subaddress 0Ch Table 50. Chrominance saturation control: decoder part; 0Ch[7:0] Gain Control bits DSAT7 1 ...
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... NXP Semiconductors Table 52. Chrominance control 1; 0Eh[7:0] Bit Description D[6:4] color standard selection in non AUTO mode D[6:4] color standard selection in AUTO mode (AUTO mode is selected, if either AUTO0 or AUTO1 is set; see below) D3 disable chrominance vertical filter and PAL phase error correction D2 fast color time constant ...
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... NXP Semiconductors 10.2.16 Subaddress 0Fh Table 53. Chrominance gain control; 0Fh[7:0] Bit Description D7 automatic chrominance gain control D[6:0] chrominance gain value (if ACGC is set to logic 1) 10.2.17 Subaddress 10h Table 54. Chrominance control 2; 10h[7:0] Bit Description D[7:6] fine offset adjustment B Y component D[5:4] fine offset adjustment ...
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... NXP Semiconductors Table 55. Mode/delay control; 11h[7:0] Bit Description D[2:0] luminance delay compensation (steps LLC) 10.2.19 Subaddress 12h Table 56. RT signal control: RTS0 output; 12h[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11h[3]]. RTS0 output 3-state Constant LOW CREF (13.5 MHz toggling pulse; see CREF2 (6.75 MHz toggling pulse ...
Page 114
... NXP Semiconductors Table 57. RT signal control: RTS1 output; 12h[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11h[6]]. RTS1 output 3-state Constant LOW CREF (13.5 MHz toggling pulse; see CREF2 (6.75 MHz toggling pulse; see [1] HL; horizontal lock indicator : unlocked locked VL ...
Page 115
... NXP Semiconductors 10.2.20 Subaddress 13h Table 58. RT/X port output control; 13h[7:0] Bit Description D7 RTCO output enable D6 X port XRH output selection D[5:4] X port XRV output selection D3 horizontal lock indicator selection D[2:0] XPD7 to XPD0 (port output format selection); see Section 9.5 SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors 10.2.21 Subaddress 14h Table 59. Analog/ADC/auto/compatibility control; 14h[7:0] Bit Description D7 compatibility bit for SAA7199 D6 update time interval for AGC value 23h[7] and analog test select 14h[5:4] D3 XTOUT output enable D2 automatic chrominance standard detection control 1 D[1:0] ADC sample clock phase delay 10 ...
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... NXP Semiconductors 10.2.23 Subaddress 16h Table 61. VGATE stop; 17h[1] and 16h[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Field Frame Decimal line value counting 50 Hz 1st 1 312 2nd 314 1st 2 0... 2nd 315 1st 312 ...310 2nd 625 60 Hz 1st 4 262 ...
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... NXP Semiconductors 10.2.25 Subaddress 18h Table 63. Raw data gain control; RAWG[7:0] 18h[7:0]; see Gain Control bits RAWG7 255 (double amplitude) 0 128 (nominal level (off) 0 10.2.26 Subaddress 19h Table 64. Raw data offset control; RAWO[7:0] 19h[7:0]; see Offset Control bits RAWO7 128 LSB ...
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... NXP Semiconductors 10.2.28 Subaddress 1Fh Table 66. Status byte 2 video decoder; 1Fh[7:5] and 1Fh[3:0]; read only register Bit Description D7 status bit for interlace detection D6 status bit for horizontal and vertical loop D5 identification bit for detected field frequency D3 Macrovision encoded color stripe burst type 3 (4 line ...
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... NXP Semiconductors 10.3.2 Subaddress 24h Table 68. Analog input control 6 (AICO6): static gain control channel 3; 23h[0] and 24h[7:0] Decimal Gain Sign bit value (dB) 23h[0] GAI38 0... 3 0 ...144 0 0 145... 0 0 ...511 +6 1 10.3.3 Subaddress 25h Table 69. Analog input control 7 (AICO7): static gain control channel 4; 23h[1] and 25h[7:0] ...
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... NXP Semiconductors Table 70. Component delay/fast switch control; 29h[7:0] Bit Description D[2:0] component input delay adjustment relative to decoded CVBS signal 10.3.5 Subaddress 2Ah Table 71. Luminance brightness control component part; 2Ah[7:0] Offset Control bits CBRI7 255 (bright) 1 128 (ITU level (dark) 0 10.3.6 Subaddress 2Bh Table 72. Luminance contrast control component part ...
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... NXP Semiconductors 10.4 Interrupt mask registers See also 10.4.1 Subaddress 2Dh Table 74. Interrupt mask 1; 2Dh[4:2] and 2Dh[1] Bit Description D4 interrupt enable ‘VPS signal detected/lost’ (corresponding flag: 60h[4]) D3 interrupt enable ‘PALplus detected/lost’ (corresponding flag: 60h[3]) MPPV D2 interrupt enable ‘closed caption detected/lost’ (corresponding flag: ...
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... NXP Semiconductors 10.5 Programming register audio clock generation See equations in 10.5.1 Subaddresses 30h to 32h Table 77. Audio master clock (AMCLK) cycles per field Subaddress Control bits 30h ACPF7 31h ACPF15 32h - 10.5.2 Subaddresses 34h to 36h Table 78. Audio master clock (AMCLK) nominal increment ...
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... NXP Semiconductors 10.6 Programming register VBI data slicer 10.6.1 Subaddress 40h Table 82. Slicer control 1; 40h[6:4] Bit Description D6 Hamming check D5 framing code error D4 amplitude searching 10.6.2 Subaddresses 41h to 57h Table 83. Line control register; LCR2 to LCR24 (41h to 57h) See Section 8.3 and Section 8 ...
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... NXP Semiconductors 10.6.4 Subaddress 59h Table 85. Horizontal offset for slicer; slicer set 59h and 5Bh Horizontal offset Recommended value 10.6.5 Subaddress 5Ah Table 86. Vertical offset for slicer; slicer set 5Ah and 5Bh Vertical offset Minimum value 0 Maximum value 312 Value for 50 Hz 625 lines input Value for 60 Hz 525 lines input 10 ...
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... NXP Semiconductors 10.6.9 Subaddress 60h Table 90. Slicer status byte 0; 60h[6:2]; read only register Bit Description D6 framing code valid D5 framing code valid D4 VPS valid D3 PALplus valid D2 closed caption valid 10.6.10 Subaddresses 61h and 62h Table 91. Slicer status byte 1; 61h[5:0] and slicer status byte 2; 62h[7:0]; read only registers ...
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... NXP Semiconductors Table 93. Global control 1; global set 80h[3:0] I port and scaler back-end clock selection ICLK output and back-end clock is line-locked clock LLC from decoder ICLK output and back-end clock is XCLK from X port ICLK output is LLC and back-end clock is LLC2 clock Back-end clock is the ICLK input IDQ pin carries the data qualifi ...
Page 128
... NXP Semiconductors Table 96. I port signal definitions; global set 84h[7:6] and 86h[5] I port signal definitions IGP0 is set to logic 0 (default polarity) IGP0 is the output FIFO almost filled flag IGP0 is the output FIFO overflow flag IGP0 is the output FIFO almost full flag, level to be programmed in subaddress 86h IGP0 is the output FIFO almost empty fl ...
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... NXP Semiconductors Table 99. X port signal definitions text slicer; global set 85h[7:5] X port signal definitions text slicer Video data limited to range 1 to 254 Video data limited to range 8 to 247 Double word byte swap, influences serial output timing SAV SAV SAV SAV [ don’ ...
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... NXP Semiconductors Table 102. I port FIFO flag control and arbitration; global set 86h[3:0] I port FIFO flag control and arbitration FAE FIFO flag almost empty level < 16 double words < 8 double words < 4 double words 0 double words FAF FIFO flag almost full level ...
Page 131
... NXP Semiconductors 10.7.3 Subaddress 88h Table 105. ADC port control; global set 88h[7:4] ADC port output control/start-up control DPROG = 0 after reset DPROG = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit PRDON; if DPROG was set to logic 1 and PRDON status bit shows a ...
Page 132
... NXP Semiconductors Table 107. Status information scaler part; 8Fh[7:0]; read only register 2 Bit I C-bus status bit D2 ERROF D1 FIDSCI D0 FIDSCO [1] Status information is unsynchronized and shows the actual status at the time of I 10.7.5 Subaddresses 90h and C0h Table 108. Task handling control; register set A [90h[7:6]] and B [C0h[7:6]] Event handler control Output fi ...
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... NXP Semiconductors 10.7.6 Subaddresses 91h to 93h Table 111. X port formats and configuration; register set A [91h[7:3]] and B [C1h[7:3]] Scaler input format and configuration source selection Only if XRQT[83h[2 scaler input source reacts on SAF7118 request Scaler input source is a continuous data stream, which cannot be ...
Page 134
... NXP Semiconductors Table 113. X port input reference signal definitions; register set A [92h[7:4]] and B [C2h[7:4]] X port input reference signal definitions XRV is a frame sync, V pulses are generated internally on both edges of FS input X port field ID is state of XRH at reference edge on XRV (defined by XFDV) Field ID (decoder and X port fi ...
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... NXP Semiconductors Table 116. I port output format and configuration; register set A [93h[4:0]] and B [C3h[4:0]] I port output formats and configuration double word formatting double word formatting only every 2nd line output only every 4th line output Y only Not defined Not defined Not defi ...
Page 136
... NXP Semiconductors Table 119. Vertical input window start; register set A [98h[7:0]; 99h[3:0]] and B [C8h[7:0]; C9h[3:0]] Vertical input acquisition window definition offset in Y (vertical) [1] direction Line offset = 0 Line offset = 1 Maximum line offset = 4095 [1] For trigger condition: STRC[1:0] 90h[1: > (number of input lines per field conditions: YO > ...
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... NXP Semiconductors Table 122. Vertical output window length; register set A [9Eh[7:0]; 9Fh[3:0]] and B [CEh[7:0]; CFh[3:0]] Vertical output acquisition window definition number of desired output lines in Y (vertical) direction No output 1 pixel Maximum possible number of output [1] lines = 4095 [1] If the desired output length is greater than the number of scaled output lines, the processing is cut. ...
Page 138
... NXP Semiconductors Table 126. Prescaler DC gain and FIR prefilter control; register set A [A2h[3:0]] and B [D2h[3:0]] Prescaler DC gain Prescaler output is renormalized by gain factor = 1 Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = ...
Page 139
... NXP Semiconductors 10.7.11 Subaddresses A8h to AEh Table 130. Horizontal luminance scaling increment; register set A [A8h[7:0]; A9h[7:0]] and B [D8h[7:0]; D9h[7:0]] Horizontal luminance Control bits scaling increment A [A9h[7:4]] B [D9h[7:4]] XSCY[15:12] 1024 Scale = (theoretical) 0000 1 zoom 1024 Scale = , lower limit 0000 294 defined by data path ...
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... NXP Semiconductors 10.7.12 Subaddresses B0h to BFh Table 134. Vertical luminance scaling increment; register set A [B0h[7:0]; B1h[7:0]] and B [E0h[7:0]; E1h[7:0]] Vertical luminance scaling Control bits increment A [B1h[7:4]] B [E1h[7:4]] YSCY[15:12] 1024 Scale = (theoretical) 0000 1 zoom 1024 Scale = zoom 0000 1023 Scale = 1, equals 1024 ...
Page 141
... NXP Semiconductors Table 138. Vertical luminance phase offset ‘00’; register set A [BCh[7:0]] and B [ECh[7:0]] Vertical luminance phase Control bits offset YPY07 Offset = Offset = = 1 line 0 32 255 Offset = lines 1 32 11. Programming start setup 11.1 Decoder part The given values force the following behavior of the SAF7118 decoder part: • ...
Page 142
... NXP Semiconductors Table 139. Decoder part start setup values for the three main standards Subaddress Register function (hexadecimal) 0F chrominance gain control 10 chrominance control 2 11 mode/delay control 12 RT signal control 13 RT/X port output control 14 analog/ADC/compatibility control 15 VGATE start, FID change 16 VGATE stop ...
Page 143
... NXP Semiconductors Table 140. Component video part and interrupt mask start setup values Subaddress Register function (hexadecimal) 2B component contrast control 2C component saturation control 2D interrupt mask 1 2E interrupt mask 2 2F interrupt mask 3 [1] All X values must be set to logic 0. 11.3 Audio clock generation part The given values force the following behavior of the SAF7118 audio clock generation part: • ...
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... NXP Semiconductors 11.4 Data slicer and data type control part The given values force the following behavior of the SAF7118 VBI data slicer part: • Closed captioning data are expected at line 21 of field 1 (60 Hz/525 line system) • All other lines are processed as active video • ...
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... NXP Semiconductors 11.5 Scaler and interfaces Table 143 • prsc = prescale ratio • fisc = fine scale ratio • vsc = vertical scale ratio The ratio is defined as: In the following settings the VBI data slicer is inactive. To activate the VBI data slicer, VITX[1:0] 86h[7:6] has to be set to ‘11’. Depending on the VBI data slicer settings, the sliced VBI data is inserted after the end of the scaled video lines, if the regions of VBI data slicer and scaler overlaps ...
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... NXP Semiconductors 11.5.3 Examples Table 143. Example of configurations Example Scaler source and reference events number 1 analog input to 8-bit I port output, with SAV/EAV codes, 8-bit serial byte stream decoder output at X port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; H and V gates on IGPH and IGPV, IGP0 = VBI sliced data fl ...
Page 147
... NXP Semiconductors Table 144. Scaler and interface configuration example 2 I C-bus Main functionality address (hex) Input and output window definition 94 horizontal input offset (XO horizontal input (source) window length (XS vertical input offset (YO vertical input (source) window length (YS horizontal output (destination) window length (XD) ...
Page 148
... NXP Semiconductors 12. Limiting values Table 145. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and grounded (0 V); all supply pins connected together. Symbol Parameter V DDD V DDA V i(A) V i( stg T amb V esd [1] Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < V [2] Class 2 according to JESD22-A114-B ...
Page 149
... NXP Semiconductors 14. Characteristics Table 147. Characteristics DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter Supplies V digital supply DDD voltage I digital supply DDD current P power dissipation D digital part V analog supply DDA voltage I analog supply DDA current P power dissipation ...
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... NXP Semiconductors Table 147. Characteristics …continued DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter 9-bit analog-to-digital converters B analog bandwidth differential phase diff G differential gain diff f ADC clock clk(ADC) frequency LE DC differential dc(d) linearity error LE DC integral linearity ...
Page 151
... NXP Semiconductors Table 147. Characteristics …continued DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter V LOW-level output OL(n) voltage all other digital outputs V HIGH-level output OH(n) voltage all other digital outputs Clock output timing (LLC and LLC2) C output load ...
Page 152
... NXP Semiconductors Table 147. Characteristics …continued DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter Crystal specification (X1) T ambient amb(X1) temperature C load capacitance L R series resonance s resistor C motional 1 capacitance C parallel 0 capacitance Crystal oscillator for 24.576 MHz f nominal frequency ...
Page 153
... NXP Semiconductors Table 147. Characteristics …continued DDD DDA levels refer to drawings and conditions illustrated in Symbol Parameter duty factors for t /t XCLKH XCLKL t rise time r t fall time f Data and control signal output timing X port, related to XCLK output (for XPCK[1:0]83h[5: default) ...
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... NXP Semiconductors clock input XCLK t SU;DAT data and control inputs (X port) input XDQ data and control outputs X port, I port clock outputs LLC, LLC2, XCLK, ICLK and ICLK input Fig 91. Data input/output timing diagram (X port, RT port and I port) SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors 15. Application information V DDD 680 BAT83 150 680 BF840 75 DGND CVBS1 CVBS2 VSB1 VSB2 EXMCLR AOUT V DDA V DDD 2 100 F F DGND AGND (1) For board design without boundary scan implementation this pin should be connected to ground. Fig 92. Application example with 24.576 MHz crystal (HBGA156 package) ...
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... NXP Semiconductors V DDD 680 BAT83 150 680 BF840 75 DGND CVBS1 CVBS2 VSB1 VSB2 EXMCLR AOUT V DDA V DDD 2 DGND AGND (1) For board design without boundary scan implementation this pin should be connected to ground. Fig 93. Application example with 24.576 MHz crystal (QFP160 package) SAF7118_4 Product data sheet Multistandard video decoder with adaptive comb fi ...
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... NXP Semiconductors SAF7118 B4(155) A3(156) XTALI XTALO 32.11 MHz 4 With 3rd harmonic quartz. Crystal load = 8 pF. SAF7118 B4(155) A3(156) XTALI 24.576 MHz 4 With 3rd harmonic quartz. Crystal load = 8 pF. SAF7118 B4(155) A3(156) XTALI XTALO 32.11 MHz or 24.576 MHz n.c. G clock g. With direct clock. ...
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... NXP Semiconductors 16. Test information 16.1 Boundary scan test The SAF7118 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAF7118 follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” set by the Joint Test Action Group (JTAG) ...
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... NXP Semiconductors When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identifi ...
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... NXP Semiconductors 17. Package outline HBGA156: plastic thermal enhanced ball grid array package; 156 balls; body 1.15 mm; heatsink ball A1 index area shape optional (4 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.5 1.25 0.6 mm 1.75 0.3 1.05 0.4 OUTLINE VERSION IEC SOT807-1 Fig 96. Package outline SOT807-1 (HBGA156) ...
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... NXP Semiconductors QFP160: plastic quad flat package; 160 leads (lead length 1.6 mm); body 3.4 mm; high stand-off height y 120 121 pin 1 index 160 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.50 3.6 mm 4.07 0.25 0.25 3.2 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 98. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Appendix 19.1 Issue 1: Bit ICKS3 = 1 (I 80h) drives image port output clock ICLK to 3-state ...
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... NXP Semiconductors 19.2 Issue 2: Forced odd/even toggle option, enabled by bit FOET = C-bus control signal, bit D5 of subaddress 08h) does not work properly Background (how it should work): Setting FOET = 1 is intended to make the odd/even output signal toggle fieldwise even if the video source is of non-interlace type. ...
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... NXP Semiconductors 19.4 Issue 4: Erase condition for interrupt pin INT_A Background (how it should work): The status flags are grouped into four 8-bit registers. The interrupt fl cleared on a read access to a status register, comprising the event that caused the interrupt. This implies that it would be sufficient to clear the interrupt by reading only those registers which have been enabled by their corresponding masks ...
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... NXP Semiconductors Workaround: It should be avoided to use the detected odd/even information whenever it cannot be assured that the input signal is of stable time base. 19.6 Issue 6: Slicing of MOJI VBI data leads to unexpected results Background (how it should work): SAF7118 incorporates a versatile VBI data slicer, for various data types, including MOJI. ...
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... NXP Semiconductors CLK # Nominal MOJI data structure AB/EC 4 programmable data 9 data 10 data 11 data 12 data 13 data 40 data 41 data 42 data check sum 51 25h BC = byte count B6/F1 Fig 99. Erroneous case table Impact: A succeeding signal processing relying on correct headers of sliced data in accordance with MOJI will be upset by the erroneous bytes, resulting in wrong character display. ...
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... NXP Semiconductors Workaround: Such error can be detected and corrected through software post-processing, by investigating the actual byte count value BC for each data packet: The entire data packet must be captured in some intermediate memory accessible to software. (The SAV and EAV sequences may get dropped, i.e. not stored in memory. ...
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... NXP Semiconductors 19.7 Issue 7: NTSC-Japan offset compensation does not work as specified in Y/C mode Background (how it should work): The difference between NTSC M and NTSC-Japan is the non-existing 7.5 IRE offset in Japan. The offset should automatically change by setting the preferred standard to NTSC-Japan instead of NTSC M via CSTD[2:0] = 100. ...
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... Document ID Release date SAF7118_4 20080704 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section 19 • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 Video acquisition/clock . . . . . . . . . . . . . . . . . . . 2 2.2 Video decoder 2.3 Component video processing . . . . . . . . . . . . . . 2 2.4 Video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.5 VBI data decoder and slicer . . . . . . . . . . . . . . . 3 2.6 Audio clock generation . . . . . . . . . . . . . . . . . . . 3 2.7 Digital I/O interfaces . . . . . . . . . . . . . . . . . . . . . 3 2.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 Ordering information ...
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... NXP Semiconductors 9.8.2 X port input timing C-bus description . . . . . . . . . . . . . . . . . . . . . 82 2 10.1 I C-bus format 10.2 I C-bus details . . . . . . . . . . . . . . . . . . . . . . . . 91 10.2.1 Subaddress 00h . . . . . . . . . . . . . . . . . . . . . . . 91 10.2.2 Subaddress 01h . . . . . . . . . . . . . . . . . . . . . . . 91 10.2.3 Subaddress 02h . . . . . . . . . . . . . . . . . . . . . . . 92 10.2.4 Subaddress 03h . . . . . . . . . . . . . . . . . . . . . . 106 10.2.5 Subaddress 04h . . . . . . . . . . . . . . . . . . . . . . 107 10.2.6 Subaddress 05h . . . . . . . . . . . . . . . . . . . . . . 107 10.2.7 Subaddress 06h . . . . . . . . . . . . . . . . . . . . . . 107 10.2.8 Subaddress 07h ...
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... NXP Semiconductors 18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 163 19 Appendix 164 19.1 Issue 1: Bit ICKS3 = 1 (I signal, bit D3 of subaddress 80h) drives image port output clock ICLK to 3-state . . . . 164 19.2 Issue 2: Forced odd/even toggle option, enabled by bit FOET = 1 (I signal, bit D5 of subaddress 08h) does not work properly ...