SAF7118EHV1 NXP Semiconductors, SAF7118EHV1 Datasheet - Page 108

• Manufacturer Part Number: SAF7118EHV1
• Manufacturer: NXP Semiconductors

Specifications of SAF7118EHV1

• Screening Level: Industrial
• Package Type: HBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 45.
Table 46.
SAF7118_4
Product data sheet
Delay time (step
size = 8 / LLC)
...108 (50 Hz)
...107 (60 Hz)
109...127 (50 Hz)
108...127 (60 Hz)
Bit
D7
D6
D5
D[4:3]
D2
D[1:0]
128... 109 (50 Hz)
128... 108 (60 Hz)
108 (50 Hz)...
107 (60 Hz)...
Horizontal sync stop; 07h[7:0]
Sync control; 08h[7:0]
Description
automatic field detection
field selection; active if
AUFD = 0
forced ODD/EVEN toggle
horizontal time constant
selection
horizontal PLL
vertical noise reduction
10.2.8 Subaddress 07h
10.2.9 Subaddress 08h
Control bits D7 to D0
HSS7
forbidden (outside available central counter range)
1
1
0
0
forbidden (outside available central counter range)
HSS6
0
0
1
1
Symbol
AUFD
FSEL
FOET
HTC[1:0]
HPLL
VNOI[1:0]
Rev. 04 — 4 July 2008
HSS5
0
0
1
1
Value
0
1
0
1
0
1
00
01
10
11
0
1
00
01
10
11
Multistandard video decoder with adaptive comb filter
HSS4
1
1
0
0
Function
field state directly controlled via FSEL
automatic field detection; recommended setting
50 Hz, 625 lines
60 Hz, 525 lines
ODD/EVEN signal toggles only with interlaced source
ODD/EVEN signal toggles fieldwise even if source is
non-interlaced
TV mode, recommended for poor quality TV signals
only; do not use for new applications
VTR mode, recommended if a deflection control circuit
is directly connected to the SAF7118
reserved
fast locking mode; recommended setting
PLL closed
PLL open; horizontal frequency fixed
normal mode; recommended setting
fast mode, applicable for stable sources only; automatic
field detection (AUFD) must be disabled
free running mode
vertical noise reduction bypassed
HSS3
0
0
1
1
HSS2
1
1
1
0
HSS1
0
0
0
1
SAF7118
© NXP B.V. 2008. All rights reserved.
HSS0
0
1
0
1
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