SAF7118EHV1 NXP Semiconductors, SAF7118EHV1 Datasheet - Page 42
SAF7118EHV1
Manufacturer Part Number
SAF7118EHV1
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAF7118EHV1.pdf
(175 pages)
Specifications of SAF7118EHV1
Screening Level
Industrial
Package Type
HBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
SAF7118_4
Product data sheet
Fig 33. Vertical timing diagram for 60 Hz/525 line systems
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of
single field counting
single field counting
V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the
slope is dependent on the internal processing delay and may change a few clock cycles from version to version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to
For further information see
ITU counting
ITU counting
F_ITU656
F_ITU656
V123
VGATE
V123
VGATE
CVBS
HREF
CVBS
HREF
FID
FID
(1)
(1)
525
262
262
262
VSTO [ 8:0 ] = 101h
VSTO [ 8:0 ] = 101h
263
263
1
1
Table
264
56,
2
2
1
Table 57
265
3
3
2
and
Rev. 04 — 4 July 2008
266
4
4
3
Table
267
5
5
4
(a) 1st field
(b) 2nd field
Multistandard video decoder with adaptive comb filter
58.
268
6
6
5
269
7
7
6
270
8
8
7
271
9
9
8
272
10
10
9
Table
. . .
. . .
. . .
. . .
VSTA [ 8:0 ] = 011h
8.
VSTA [ 8:0 ] = 011h
284
SAF7118
21
21
21
© NXP B.V. 2008. All rights reserved.
mhb541
285
22
22
22
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