SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 3

• Manufacturer Part Number: SAA7118E
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7118_7
Product data sheet
2.4 Video scaler
2.5 VBI data decoder and slicer
2.6 Audio clock generation
2.7 Digital I/O interfaces
2.8 Miscellaneous
I
I
I
I
I
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I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Horizontal and vertical downscaling and upscaling to randomly sized windows
Horizontal and vertical scaling range: variable zoom to
that the H and V zoom are restricted by the transfer data rates)
Anti-alias and accumulating filter for horizontal scaling
Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing
(6-bit phase accuracy)
Horizontal phase correct up and downscaling for improved signal quality of scaled
data, especially for compression and video phone applications, with 6-bit phase
accuracy (1.2 ns step width)
Two independent programming sets for scaler part, to define two ‘ranges’ per field or
sequences over frames
Fieldwise switching between decoder part and expansion port (X port) input
Brightness, contrast and saturation controls for scaled outputs
Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for
World Standard Teletext (WST), North American Broadcast Text System (NABTS),
closed caption, Wide Screen Signalling (WSS), etc.
Generation of a field-locked audio master clock to support a constant number of audio
clocks per video field
Generation of an audio serial and left/right (channel) clock signal
Real-time signal port (R port), inclusive continuous line-locked reference clock and
real-time status information supporting RTC level 3.1 (refer to document
“RTC Functional Specification” for details)
Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-C
Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in
master mode (own clock), or slave mode (external clock), with auxiliary timing and
handshake signals
Discontinuous data streams supported
32-word
28-word
Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-C
Scaled 8-bit luminance only and raw CVBS data output
Sliced, decoded VBI data output
Power-on control
5 V tolerant digital inputs and I/O ports
N
N
Output from decoder part, real-time and unscaled
Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
4-byte FIFO register for video output data
4-byte FIFO register for decoded VBI data output
Rev. 07 — 7 July 2008
Multistandard video decoder with adaptive comb filter
B
-C
R
output
1
64
(icon) (it should be noted
SAA7118
© NXP B.V. 2008. All rights reserved.
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