SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 69

• Manufacturer Part Number: SAA7118E
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7118_7
Product data sheet
8.7.2 Signals ASCLK and ALRCLK
8.7.3 Other control signals
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital
audio signal transmission and for channel-select. The frequencies of these signals are
defined by the following parameters:
See
Table 23.
Further control signals are available to define reference clock edges and vertical
references; see
Table 24.
AMXCLK
(MHz)
12.288
11.2896
8.192
Signal
APLL[3Ah[3]]
AMVR[3Ah[2]]
LRPH[3Ah[1]]
SCPH[3Ah[0]]
•
•
SDIV[5:0] 38h[5:0] according to the equation:
LRDIV[5:0] 39h[5:0] according to the equation:
SDIV[5:0]
LRDIV[5:0]
Table 23
Programming examples for ASCLK/ALRCLK clock generation
Control signals for reference clock edges and vertical references
ASCLK
(kHz)
1536
768
1411.2
2822.4
1024
2048
for examples.
=
Table
Description
Audio PLL mode
Audio Master clock Vertical Reference
ALRCLK phase
ASCLK phase
=
f
------------------ - 1
2f
AMXCLK
0 = PLL closed
1 = PLL open
0 = internal V
1 = external V
0 = invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1 = don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
0 = invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1 = don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK
-------------------- -
2f
ASCLK
f
ASCLK
ALRCLK
24.
Rev. 07 — 7 July 2008
–
SDIV
Decimal
3
7
3
1
3
1
Multistandard video decoder with adaptive comb filter
Hex
03
07
03
01
03
01
f
ASCLK
f
ALRCLK
(kHz)
48
44.1
32
ALRCLK
=
----------------------------------- -
=
SDIV
------------------------- -
LRDIV 2
f
AMXCLK
f
LRDIV
Decimal
16
8
16
32
16
32
ASCLK
+
1
SAA7118
© NXP B.V. 2008. All rights reserved.
2
Hex
10
08
10
10
10
10
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