MT47H32M16HR-37E:F Micron Technology Inc, MT47H32M16HR-37E:F Datasheet - Page 24

MT47H32M16HR-37E:F

Manufacturer Part Number
MT47H32M16HR-37E:F
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet

Specifications of MT47H32M16HR-37E:F

Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
205mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT47H32M16HR-37E:F
Manufacturer:
MICRON
Quantity:
5 373
Electrical Specifications – I
I
Table 8: General I
I
Table 9: I
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
I
CL (I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Speed Grade
Timing patterns for 4-bank x4/x8/x16 devices
-5E
-37E
-3
-3E
-25
-25E
-187E
DD
DD7
DD
RCD (I
RC (I
RRD (I
RRD (I
CK (I
RAS MIN (I
RAS MAX (I
RP (I
RFC (I
RFC (I
RFC (I
RFC (I
FAW (I
FAW (I
Parameters
DD
Specifications and Conditions
DD
DD
DD
Conditions
DD
DD
DD
DD
)
DD
DD
DD
DD
DD
)
)
)
)
) - x4/x8 (1KB)
) - x16 (2KB)
- 256Mb)
- 512Mb)
- 1Gb)
- 2Gb)
) - x4/x8 (1KB)
) - x16 (2KB)
DD7
DD
DD
)
)
Timing Patterns (4-Bank Interleave READ Operation)
I
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D
DD7
DD
Notes:
Parameters
Timing Patterns
The detailed timings are shown below for I
General Parameters Table conflict with pattern requirements in the I
terns Table, then the I
1. A = active; RA = read auto precharge; D = deselect.
2. All banks are being interleaved at
3. Control and address bus inputs are stable during DESELECTs.
13.125
58.125
70,000
13.125
-187E
1.875
127.5
197.5
105
7.5
10
45
75
7
DD
70,000
127.5
197.5
-25E
12.5
57.5
12.5
105
Parameters
7.5
2.5
10
45
75
5
DD7
timing patterns requirements take precedence.
Defined by pattern in on page
Defined by pattern in on page
70,000
24
127.5
197.5
105
-25
7.5
2.5
15
60
10
45
15
75
6
Electrical Specifications – I
t
RC (I
Micron Technology, Inc. reserves the right to change products or specifications without notice.
70,000
127.5
197.5
105
-3E
7.5
12
57
10
45
12
75
4
3
DD
DD7
512Mb: x4, x8, x16 DDR2 SDRAM
) without violating
. Where general I
70,000
127.5
197.5
105
7.5
15
60
10
45
15
75
-3
5
3
70,000
127.5
197.5
-37E
3.75
105
© 2004 Micron Technology, Inc. All rights reserved.
7.5
15
60
10
45
15
75
t
4
DD
RRD (I
parameters in the
DD
DD7
DD
70,000
) using a BL = 4.
127.5
197.5
105
-5E
7.5
Parameters
15
55
10
40
15
75
Timing Pat-
3
5
Units
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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