MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 117

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

REFRESH
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
charge. A READ or WRITE command to a different bank is allowed during concurrent
auto precharge as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Input A10 determines whether one or all
banks are precharged. In the case where only one bank is precharged, inputs BA[2:0]
select the bank; otherwise, BA[2:0] are treated as “Don’t Care.”
After a bank is precharged, it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A PRECHARGE command is treated as
a NOP if there is no open row in that bank (idle state) or if the previously open row is
already in the process of precharging. However, the precharge period is determined by
the last PRECHARGE command issued to the bank.
REFRESH is used during normal operation of the DRAM and is analogous to CAS#-before-
RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be
issued each time a refresh is required. The addressing is generated by the internal re-
fresh controller. This makes the address bits a “Don’t Care” during a REFRESH com-
mand. The DRAM requires REFRESH cycles at an average interval of 7.8µs (maximum
when T
when the REFRESH command is registered and ends
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight REFRESH com-
mands can be posted to any given DRAM, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH command is nine times the
maximum average interval refresh rate. Self refresh may be entered with up to eight RE-
FRESH commands being posted. After exiting self refresh (when entered with posted
REFRESH commands) additional posting of REFRESH commands is allowed to the ex-
tent the maximum number of cumulative posted REFRESH commands (both pre and
post self refresh) does not exceed eight REFRESH commands.
The posting limit of eight REFRESH commands is a JEDEC specification; however, as
long as all the required number of REFRESH commands are issued within the refresh
period (64ms), exceeding the eight posted REFRESH commands is allowed.
C
≤ +85°C or 3.9µs; maximum when T
117
Micron Technology, Inc. reserves the right to change products or specifications without notice.
C
≤ +95°C). The REFRESH period begins
2Gb: x4, x8, x16 DDR3 SDRAM
t
RFC (MIN) later.
© 2006 Micron Technology, Inc. All rights reserved.
Commands