GS832272C-250I GSI TECHNOLOGY, GS832272C-250I Datasheet

GS832272C-250I

Manufacturer Part Number

GS832272C-250I

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS832272C-250I.pdf (46 pages)

Specifications of GS832272C-250I

Density

36Mb

Access Time (max)

6.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

153.8MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

19b

Package Type

FBGA

Operating Temp Range

-40C to 85C

Number Of Ports

Supply Current

285mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

209

Word Size

72b

Number Of Words

512K

Lead Free Status / RoHS Status

Not Compliant

Current page: 1 of 46
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119-, 165-, & 209-Pin BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V +10%/–10% core power supply

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package

• RoHS-compliant packages available

Functional Description

Applications

The GS832218/36/72 is a

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

Rev: 1.07a 12/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

37,748,736 -bit high performance

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

36Mb S/DCD Sync Burst SRAMs

2M x 18, 1M x 36, 512K x 72

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

(x18/x36)

tCycle

(x72)

Parameter Synopsis

1/46

-250 -225 -200 -166 -150 -133 Unit

285

350

440

205

235

315

2.5

3.0

4.0

6.5

265

320

410

195

225

295

2.7

3.0

4.4

7.0

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS832218/36/72 is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

245

295

370

185

210

265

GS832218(B/E)/GS832236(B/E)/GS832272(C)

3.0

5.0

7.5

220

260

320

175

200

255

3.5

6.0

8.0

210

240

300

165

190

240

3.8

6.7

8.5

185

215

265

155

175

230

4.0

7.5

8.5

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS832272C-250I

GS832272C-250I Summary of contents

Page 1

... Curr (x72) 315 295 265 255 1/46 250 MHz–133 MHz 3.3 V I/O 3.8 4.0 ns 3.8 4.0 ns 6.7 7.5 ns 210 185 mA 240 215 mA 300 265 mA 8.5 8.5 ns 8.5 8.5 ns 165 155 mA 190 175 mA 240 230 mA © 2001, GSI Technology DD ...

Page 2

Page 3

... FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock 3/46 I/Os; active low B I/Os; active low I/Os; active low G H © 2001, GSI Technology ...

Page 4

... GS832272 209-Bump BGA Pin Description (Continued) Symbol Type DDQ Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) Description Core power supply I/O and Core Ground Output driver power supply 4/46 © 2001, GSI Technology ...

Page 5

... E3 BW ADSC TDI A1 TDO A A TMS A0 TCK A 5/ ADV ADSP DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2001, GSI Technology ...

Page 6

... TDI A1 TDO A A TMS A0 TCK A 6/ ADV ADSP DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2001, GSI Technology ...

Page 7

... Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low Single Cycle Deselect/Dual Cyle Deselect Mode Control Core power supply I/O and Core Ground Output driver power supply 7/46 I/Os; active low (x36 Version) D © 2001, GSI Technology ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) 119-Bump BGA—x36 Common I/O—Top View ADSP ADSC DQP ADV SCD DQP LBO TMS TDI TCK TDO 2 Body—1.27 mm Bump Pitch 8/ DDQ DQP DDQ DDQ DDQ DQP DDQ © 2001, GSI Technology ...

Page 9

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) 119-Bump BGA—x18 Common I/O—Top View ADSP ADSC ADV SCD DQP LBO TMS TDI TCK TDO 2 Body—1.27 mm Bump Pitch 9/ DDQ DQP DDQ DDQ DDQ DDQ © 2001, GSI Technology ...

Page 10

... Single Cycle Deselect/Dual Cyle Deselect Mode Control Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground I/O and Core Ground Output driver power supply 10/46 I/Os; active low D © 2001, GSI Technology ...

Page 11

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) GS832218/36 Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q SCD 11/46 A Memory Array DQx1–DQx9 © 2001, GSI Technology ...

Page 12

... High Drive (Low Impedance Low Drive (High Impedance) I nterleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 12/ A[1:0] A[1:0] A[1:0] A[1: © 2001, GSI Technology BPR 1999.05.18 ...

Page 13

... C D Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272( may be used in any combination with BW to write single or multiple bytes. D 13/ Notes and/ © 2001, GSI Technology ...

Page 14

... Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) State Diagram ADSP ADSC Key 14/46 ADV High High High High High © 2001, GSI Technology ...

Page 15

... ADSP is tied high and ADV is tied low. Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) Simplified State Diagram X Deselect First Write Burst Write CR CW 15/ First Read Burst Read BW, and GW) control inputs, and © 2001, GSI Technology ...

Page 16

... Data Input Set Up Time. Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) Simplified State Diagram with G X Deselect First Write Burst Write 16/ First Read Burst Read CR © 2001, GSI Technology ...

Page 17

... Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2001, GSI Technology Unit Notes ...

Page 18

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 18/46 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2001, GSI Technology ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ V /2 DDQ Fig. 1 Output Load 1 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance 19/46 20% tKC DD IL Typ. Max. Unit © 2001, GSI Technology ...

Page 20

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... Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) 21/46 © 2001, GSI Technology ...

Page 22

... GSI Technology -133 Unit — ns 4.0 ns 4.0 ns — ns — ns — ns — ns — ns 8.5 ns — — — ns — ns — ...

Page 23

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 23/46 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2001, GSI Technology Deselect tKQX tHZ ...

Page 24

... Flow Through Mode Timing (SCD) Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 24/46 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2001, GSI Technology tKQX ...

Page 25

... Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 25/46 Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2001, GSI Technology tKQX ...

Page 26

... Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 26/46 Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2001, GSI Technology ...

Page 27

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) Sleep Mode Timing tKH tKH tKC tKC tKL tKL tZZS tZZH 27/46 2. The duration of SB tZZR . The JTAG output DD . TDO should be left unconnected. SS © 2001, GSI Technology ...

Page 28

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) Description 28/46 © 2001, GSI Technology ...

Page 29

... GS832218(B/E)/GS832236(B/E)/GS832272(C) JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 29/46 · · TDO © 2001, GSI Technology ...

Page 30

... TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) Not Used Configuration 30/46 GSI Technology I/O JEDEC Vendor ID Code © 2001, GSI Technology ...

Page 31

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 31/46 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2001, GSI Technology ...

Page 32

... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) Description 32/46 Notes © 2001, GSI Technology ...

Page 33

... V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC. DDn supply. DDQ 33/46 Min. Max. Unit Notes –0.3 DD –300 1 uA 100 uA –1 – 1.7 V — — 0.4 V – 100 mV V — DDQ 100 mV V — © 2001, GSI Technology ...

Page 34

... DD3 0.8 V –0.3 0 +0.3 V DD2 DD2 0 –0.3 DD2 –300 1 uA 100 uA –1 – 1.7 V — 0.4 V — – 100 mV — V DDQ 100 mV V — JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 2001, GSI Technology ...

Page 35

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit — — — — — — ns 35/46 tTKL tTKL © 2001, GSI Technology ...

Page 36

... BGA Package Drawing (Package ∅b e Max Units Symbol 22.1 mm aaa 36/ Side View Bottom View Min Typ Max — 18.0 (BSC) — 13.9 14.0 14.1 — 10.0 (BSC) — — 1.00 (BSC) — — 0.15 — © 2001, GSI Technology Units ...

Page 37

... Package Dimensions—119-Bump FPBGA (Package B, Variation 2 A1 TOP VIEW SEATING PLANE C Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0.10 A 0.20(4x) 37/ 1.27 © 2001, GSI Technology ...

Page 38

... Package Dimensions—165-Bump FPBGA (Package E; Variation 1) A1 TOP VIEW SEATING PLANE C Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832218(B/E)/GS832236(B/E)/GS832272(C) BOTTOM VIEW Ø0. Ø0. Ø0.44~0.64(165x 1.0 10.0 15±0.05 B 0.20(4x) 38/ 1.0 © 2001, GSI Technology ...

Page 39

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07a 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 40

... Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number GS832236E-133 512K x 72 GS832272C-250 512K x 72 GS832272C-225 512K x 72 GS832272C-200 512K x 72 GS832272C-166 512K x 72 GS832272C-150 512K x 72 GS832272C-133 GS832218B-250I GS832218B-225I GS832218B-200I GS832218B-166I GS832218B-150I GS832218B-133I GS832218E-250I GS832218E-225I GS832218E-200I GS832218E-166I GS832218E-150I ...

Page 41

... Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number GS832236E-250I GS832236E-225I GS832236E-200I GS832236E-166I GS832236E-150I GS832236E-133I 512K x 72 GS832272C-250I 512K x 72 GS832272C-225I 512K x 72 GS832272C-200I 512K x 72 GS832272C-166I 512K x 72 GS832272C-150I 512K x 72 GS832272C-133I GS832218GB-250 GS832218GB-225 GS832218GB-200 GS832218GB-166 GS832218GB-150 GS832218GB-133 ...

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... Updated format Content/Format • Added missing tH (Pipeline Characteristics table • Corrected note 1 on table on page 33 Content/Format • Corrected mechanical drawings • RoHS-compliant information added Content • (Rev. 1.07a: Removed Preliminary banner due to production status) 46/46 Page;Revisions;Reason © 2001, GSI Technology ...

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