GS832272C-250I GSI TECHNOLOGY, GS832272C-250I Datasheet - Page 27

• Manufacturer Part Number: GS832272C-250I
• Manufacturer: GSI TECHNOLOGY

Specifications of GS832272C-250I

• Density: 36Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 153.8MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 8
• Supply Current: 285mA
• Operating Supply Voltage (min): 2.3/3V
• Operating Supply Voltage (max): 2.7/3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 209
• Word Size: 72b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Not Compliant

Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
drivers are powered by V
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
Rev: 1.07a 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ADSC
ADSP
CK
ZZ
DDQ
Setup
Hold
.
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
tKC
tKC
tKH
tKH
tKL
tKL
Sleep Mode Timing
27/46
tZZS
tZZH
GS832218(B/E)/GS832236(B/E)/GS832272(C)
DD
or V
SS
. TDO should be left unconnected.
tZZR
DD
. The JTAG output
SB
© 2001, GSI Technology
2. The duration of