ISP1181ADGG STEricsson, ISP1181ADGG Datasheet - Page 38
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ISP1181ADGG
Manufacturer Part Number
ISP1181ADGG
Description
Manufacturer
STEricsson
Datasheet
1.ISP1181ADGG.pdf
(71 pages)
Specifications of ISP1181ADGG
Lead Free Status / RoHS Status
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Manufacturer
Quantity
Price
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Part Number:
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Philips Semiconductors
Table 38:
9397 750 13959
Product data
Bit
Symbol
Reset
Access
Lock Register: bit allocation
15
W
1
12.3.2 Unlock Device
Table 36:
Table 37:
This command unlocks the ISP1181A from write-protection mode after a ‘resume’. In
‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption
by external devices during a ‘resume’. Also, the register access for reading is possible
only after the ‘Unlock Device’ command is executed.
After waking up from ‘suspend’ state, the firmware must unlock the registers and
FIFOs via this command, by writing the unlock code (AA37H) into the Lock Register
(8-bit bus: lower byte first). The bit allocation of the Lock Register is given in
Code (Hex): B0 — unlock the device
Transaction — write 2 bytes (unlock code)
Bit
5
4 to 1
0
Error code
(Binary)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
14
W
0
Transaction error codes
Error Code Register: bit description
Symbol
-
ERROR[3:0]
RTOK
Description
no error
PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0
PID unknown; encoding is valid, but PID does not exist
unexpected packet; packet is not of the expected type (token, data, or
acknowledge), or is a SETUP token to a non-control endpoint
token CRC error
data CRC error
time-out error
babble error
unexpected end-of-packet
sent or received NAK (Not AcKnowledge)
sent Stall; a token was received, but the endpoint was stalled
overflow; the received packet was larger than the available buffer space
sent empty packet (ISO only)
bit stuffing error
sync error
wrong (unexpected) toggle bit in DATA PID; data was ignored
13
W
1
Rev. 05 — 08 December 2004
UNLOCKH[7:0] = AAH
Description
reserved
Error code. For error description, see
A logic 1 indicates that data was received or transmitted
successfully.
12
W
0
11
W
1
Full-speed USB peripheral controller
…continued
10
W
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
ISP1181A
W
9
1
37.
Table
W
8
0
37 of 70
38.