ISP1181ADGG STEricsson, ISP1181ADGG Datasheet - Page 52
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ISP1181ADGG
Manufacturer Part Number
ISP1181ADGG
Description
Manufacturer
STEricsson
Datasheet
1.ISP1181ADGG.pdf
(71 pages)
Specifications of ISP1181ADGG
Lead Free Status / RoHS Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1181ADGG
Manufacturer:
EBM
Quantity:
2 000
Part Number:
ISP1181ADGG
Manufacturer:
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Quantity:
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Philips Semiconductors
Table 57:
[1]
9397 750 13959
Product data
Symbol
Read timing (see
t
t
t
t
t
t
t
t
Write timing (see
t
t
t
t
t
t
t
t
ALE timing (see
t
t
t
RHAX
AVRL
SHDZ
RHSH
RLRH
RLDV
SHRL
SHRL
WHAX
AVWL
SHWL
SHWL
WLWH
WHSH
DVWH
WHDZ
LH
AVLL
LLAX
Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Configuration require 180 ns to complete.
+t
+t
RLRH
WLWH
Dynamic characteristics: parallel interface timing
Parameter
address hold time after RD
HIGH
address setup time before RD
LOW
data outputs high-impedance
time after CS HIGH
chip deselect time after RD
HIGH
RD pulse width
data valid time after RD LOW
CS HIGH until next ISP1181A
RD
read cycle time
address hold time after WR
HIGH
address setup time before WR
LOW
CS HIGH until next ISP1181A
WR
write cycle time
WR pulse width
chip deselect time after WR
HIGH
data setup time before WR
HIGH
data hold time after WR HIGH
ALE pulse width
address setup time before ALE
LOW
address hold time after ALE
LOW
Figure
Figure
Figure
20.1 Parallel I/O timing
20)
18)
19)
Conditions
reading
writing
Rev. 05 — 08 December 2004
8-bit bus
Min
0
0
-
0
25
-
60
90
1
0
60
90/180
22
0
5
3
20
10
0
0
[1]
Full-speed USB peripheral controller
Max
-
-
3
-
-
22
-
-
-
-
-
-
-
-
-
-
-
-
10
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
16-bit bus
Min
0
0
-
0
25
-
120
180
1
0
120
180
22
0
5
3
20
10
0
0
ISP1181A
Max
-
-
3
-
-
22
-
-
-
-
-
-
-
-
-
-
-
-
10
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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