ISP1181ADGG STEricsson, ISP1181ADGG Datasheet - Page 42

• Manufacturer Part Number: ISP1181ADGG
• Manufacturer: STEricsson

Specifications of ISP1181ADGG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
13. Interrupts
9397 750 13959
Product data
Table 49:
Figure 8
is logged in a status bit of the Interrupt Register. Corresponding bits in the Interrupt
Enable Register determine whether or not an event will generate an interrupt.
Interrupts can be masked globally by means of the INTENA bit of the Mode Register
(see
The active level and signalling mode of the INT output is controlled by the INTPOL
and INTLVL bits of the Hardware Configuration Register (see
settings after reset are active LOW and level mode. When pulse mode is selected, a
pulse of 166 ns is generated when the OR-ed combination of all interrupt bits
changes from logic 0 to logic 1.
Bit
8
7
6
5
4
3
2
1
0
Table
shows the interrupt logic of the ISP1181A. Each of the indicated USB events
19).
Interrupt Register: bit description
Symbol
EP0OUT
BUSTATUS
-
PSOF
SOF
EOT
SUSPND
RESUME
RESET
Rev. 05 — 08 December 2004
Description
A logic 1 indicates the interrupt source: control OUT endpoint.
It monitors the current USB bus status (0 = awake,
1 = suspend).
reserved
A logic 1 indicates that an interrupt is issued every 1 ms
because of the Pseudo SOF; after 3 missed SOFs ‘suspend’
state is entered.
A logic 1 indicates that a SOF condition was detected.
A logic 1 indicates that an internal EOT condition was generated
by the DMA Counter reaching zero.
A logic 1 indicates that an ‘awake’ to ‘suspend’ change of state
was detected on the USB bus.
A logic 1 indicates that a ‘resume’ state was detected.
A logic 1 indicates that a bus reset condition was detected.
…continued
Full-speed USB peripheral controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
ISP1181A
21). Default
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