MC9S08SH16CTL Freescale, MC9S08SH16CTL Datasheet
MC9S08SH16CTL
Specifications of MC9S08SH16CTL
Available stocks
Related parts for MC9S08SH16CTL
MC9S08SH16CTL Summary of contents
Page 1
... MC9S08SH32 MC9S08SH16 Data Sheet HCS08 Microcontrollers MC9S08SH32 Rev. 2 4/2008 freescale.com PRELIMINARY ...
Page 2
PRELIMINARY ...
Page 3
MC9S08SH32 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Support for interrupt/reset sources On-Chip Memory • FLASH read/program/erase over full operating ...
Page 4
PRELIMINARY ...
Page 5
... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. MC9S08SH32 Data Sheet Covers MC9S08SH32 PRELIMINARY MC9S08SH16 MC9S08SH32 Rev. 2 4/2008 ...
Page 6
... Corrected the SPI block module version. Removed incorrect ADC temper- 2 4/2008 ature sensor value from the Features section. Updated the package information with a sample mask set identifier. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. This product incorporates SuperFlash 6 Description of Changes ® ...
Page 7
... Serial Communications Interface (S08SCIV4)..................... 203 Chapter 15 Serial Peripheral Interface (S08SPIV3) ................................ 223 Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) ......................... 239 Chapter 17 Development Support ........................................................... 265 Appendix A Electrical Characteristics...................................................... 287 Appendix B Ordering Information and Mechanical Drawings................ 315 Freescale Semiconductor List of Chapters MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY 7 ...
Page 8
PRELIMINARY ...
Page 9
... MC9S08SH32 Series Memory Map ............................................................................................... 37 4.2 Reset and Interrupt Vector Assignments ......................................................................................... 38 4.3 Register Addresses and Bit Assignments........................................................................................ 39 4.4 RAM................................................................................................................................................ 46 4.5 FLASH ............................................................................................................................................ 46 4.5.1 Features ............................................................................................................................. 47 4.5.2 Program and Erase Times ................................................................................................. 47 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 Modes of Operation Chapter 4 Memory MC9S08SH32 Series Data Sheet, Rev ...
Page 10
... System Power Management Status and Control 1 Register (SPMSC1) ........................... 72 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) ........................... 73 6.1 Port Data and Data Direction .......................................................................................................... 75 6.2 Pull-up, Slew Rate, and Drive Strength........................................................................................... 76 10 Title Chapter 5 Chapter 6 Parallel Input/Output Control MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Page Freescale Semiconductor ...
Page 11
... BGND Instruction........................................................................................................... 101 7.5 HCS08 Instruction Set Summary .................................................................................................. 102 Analog Comparator 5-V (S08ACMPV3) 8.1 Introduction ................................................................................................................................... 113 8.1.1 ACMP Configuration Information .................................................................................. 113 8.1.2 ACMP/TPM Configuration Information......................................................................... 113 Freescale Semiconductor Title Chapter 7 Chapter 8 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Page 11 ...
Page 12
... Input Select and Pin Control ........................................................................................... 137 9.4.3 Hardware Trigger ............................................................................................................ 137 9.4.4 Conversion Control ......................................................................................................... 137 9.4.5 Automatic Compare Function......................................................................................... 140 9.4.6 MCU Wait Mode Operation............................................................................................ 140 12 Title Chapter 9 ) .................................................................................................. 127 DDAD )................................................................................................. 127 SSAD ) ................................................................................... 127 REFH )..................................................................................... 127 REFL MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Page Freescale Semiconductor ...
Page 13
... Address Detect Interrupt ................................................................................................. 164 10.6.3 Arbitration Lost Interrupt................................................................................................ 164 10.7 Initialization/Application Information .......................................................................................... 166 Internal Clock Source (S08ICSV2) 11.1 Introduction ................................................................................................................................... 169 11.1.1 Module Configuration..................................................................................................... 169 11.1.2 Features ........................................................................................................................... 171 11.1.3 Block Diagram ................................................................................................................ 171 Freescale Semiconductor Title Chapter 10 Chapter 11 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Page 13 ...
Page 14
... Block Diagram ................................................................................................................ 196 13.2 External Signal Description .......................................................................................................... 196 13.3 Register Definition ........................................................................................................................ 196 13.3.1 RTC Status and Control Register (RTCSC).................................................................... 197 13.3.2 RTC Counter Register (RTCCNT).................................................................................. 198 14 Title Chapter 12 Modulo Timer (S08MTIMV1) Chapter 13 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Page Freescale Semiconductor ...
Page 15
... SS — Slave Select........................................................................................................... 228 15.3 Modes of Operation....................................................................................................................... 229 15.3.1 SPI in Stop Modes .......................................................................................................... 229 15.4 Register Definition ........................................................................................................................ 229 15.4.1 SPI Control Register 1 (SPIxC1) .................................................................................... 229 15.4.2 SPI Control Register 2 (SPIxC2) .................................................................................... 230 Freescale Semiconductor Title Chapter 14 Chapter 15 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 16
... The Differences from TPM v2 to TPM v3.................................................................................... 262 17.1 Introduction ................................................................................................................................... 265 17.1.1 Forcing Active Background ............................................................................................ 265 17.1.2 Features ........................................................................................................................... 266 17.2 Background Debug Controller (BDC) .......................................................................................... 266 17.2.1 BKGD Pin Description ................................................................................................... 267 16 Title Chapter 16 Chapter 17 Development Support MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Page Freescale Semiconductor ...
Page 17
... A.14 EMC Performance..........................................................................................................................313 A.14.1 Radiated Emissions..........................................................................................................313 A.14.2 Conducted Transient Susceptibility .................................................................................313 Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................315 B.1.1 Device Numbering Scheme .............................................................................................315 B.2 Mechanical Drawings.....................................................................................................................316 Freescale Semiconductor Title Appendix A Electrical Characteristics Appendix B MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 18
PRELIMINARY ...
Page 19
... ACMP ADC channels DBG ICS IIC IRQ MTIM Pin Interrupts 1 Pin I/O RTC SCI SPI TPM1 channels TPM2 channels XOSC 1 Port I/O count does not include the output-only PTA4/ACMPO/BKGD/MS. Freescale Semiconductor t 9S08SH32 32768 1024 yes yes yes yes yes yes 8 23 ...
Page 20
... PTA2/PIA2/SD/ADP2 SDA PTA1/PIA1/TPM2CH0/ADP1/ACMP– SS PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD PTB5/TPM1CH1/SS TCLK PTB4/TPM2CH1/MISO TPM1CH0 PTB3/PIB3/MOSI/ADP7 TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 and V respectively Freescale Semiconductor ...
Page 21
... Central Processor Unit Inter-Integrated Circuit Internal Clock Source Low Power Oscillator Modulo Timer On-Chip In-Circuit Emulator Real-Time Counter Serial Peripheral Interface Serial Communications Interface Timer Pulse Width Modulator Freescale Semiconductor Table 1-2. Module Versions Module (ACMP) (ADC) (CPU) (IIC) (ICS) (XOSC) (MTIM) ...
Page 22
... MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY MTIM SCI SPI IIC FLASH ADC ADC has min and max FLASH has frequency frequency requirements. requirements for program See the ADC chapter and erase operation. See and electricals appendix the electricals appendix for details. for details. Freescale Semiconductor ...
Page 23
... MC9S08SH32 Series devices. PTC5/ADP13 PTC4/ADP12 PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS V DDA V SSA PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/ADP11 PTC2/ADP10 PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS V PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/ADP11 PTC2/ADP10 Freescale Semiconductor 28 1 PTC6/ADP14 2 27 PTC7/ADP15 26 3 PTA0/PIA0/TPM1CH0/ADP0/ACMP PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA2/PIA2/SDA/ADP2 PTA3/PIA3/SCL/ADP3 REFH 22 ...
Page 24
... Chapter 2 Pins and Connections PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO 24 PTA0/PIA0/TPM1CH0/ADP0/ACMP PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA2/PIA2/SDA/ADP2 PTA3/PIA3/SCL/ADP3 PTB0/PIB0/RxD/ADP4 6 11 PTB1/PIB1/TxD/ADP5 7 10 PTB2/PIB2/SPSCK/ADP6 8 9 PTB3/PIB3/MOSI/ADP7 Figure 2-3. 16-Pin TSSOP MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 25
... RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. BDM can be entered by holding MS low during POR or writing BDFR in SBDFR with MS low after issuing BDM command filter on RESET pin recommended for noisy environments. 4. For the 16-pin and 20-pin packages When PTA4 is configured as BKGD, pin becomes bi-directional. Freescale Semiconductor MC9S08SH32 BKGD/MS PORT A ...
Page 26
... V SSA REFL Chapter 11, “Internal Clock Source (when used) and R S MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY pins are the voltage reference high and shares the V DDA pin and these pins are available only pin. SS should be low-inductance F Freescale Semiconductor REFH ...
Page 27
... POR or force BDC reset debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a background debug force reset, which will force the MCU to active background mode. Freescale Semiconductor NOTE DD level an external pullup should ...
Page 28
... PTA7-PTA6 pins to outputs so the pins do not float. When using the 16-pin devices, the user must either enable on-chip pullup devices or change the direction of non-bonded out PTC7-PTC0 and PTA7-PTA6 pins to outputs so the pins do not float. 28 Control.” NOTE MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Section Freescale Semiconductor ...
Page 29
... PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out. 5 TPM2CHx pins can be repositioned using T2CHxPS bits in SOPT2, default reset locations are PTA1, PTB4 ACMP and ADC are both enabled, both will have access to the pin. Freescale Semiconductor Priority Lowest Port Pin Alt 1 ...
Page 30
... Chapter 2 Pins and Connections 30 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 31
... When encountering a BDC breakpoint • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY (SBDFR)”) 31 ...
Page 32
... MCU is operated in run mode for the first time. When the MC9S08SH32 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...
Page 33
... STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. Freescale Semiconductor Table 3-1. Stop Mode Selection PPDC x Stop modes disabled ...
Page 34
... Refer to Mode,” and Section 3.6.1, “Stop3 34 Mode,” for specific information on system behavior in stop modes. MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Table 3-1. Most is below the LVD DD Section 3.6.2, “Stop2 Freescale Semiconductor ...
Page 35
... Voltage regulator will BDM is enabled or if LVD is enabled when entering stop3. 7 ERCLKEN and EREFSTEN set in ICSC2, else in standby. For high frequency range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3. Freescale Semiconductor Table 3-2. Stop Mode Behavior Mode Stop2 Off ...
Page 36
... Chapter 3 Modes of Operation 36 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 37
... Nonvolatile registers (0xFFB0 through 0xFFBF) 0x0000 DIRECT PAGE REGISTERS 0x007F 0x0080 0x047F 0x0480 0x17FF 0x1800 HIGH PAGE REGISTERS 0x185F 0x1860 0x7FFF 0x8000 0xFFFF Freescale Semiconductor 0x0000 0x007F 0x0080 RAM 1024 BYTES 0x047F 0x0480 UNIMPLEMENTED 4992 BYTES 0x17FF 0x1800 0x185F 0x1860 UNIMPLEMENTED ...
Page 38
... Chapter 4 Memory 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08SH32 Series. Address (High/Low) 0xFFC0:0xFFC1 0xFFC2:0xFFC3 ...
Page 39
... Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. Freescale Semiconductor can use the more efficient direct addressing mode, which requires 4-4, the whole address in column one is shown in bold. In MC9S08SH32 Series Data Sheet, Rev ...
Page 40
... PS CLKSA PS2 PS1 ELS0B ELS0A ELS1B ELS1A Freescale Semiconductor Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 — 0 — — ACMOD0 — — ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 — IRQMOD — 0 PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 ...
Page 41
... Reserved 0x005F — 0x0060 TPM2SC TOF 0x0061 TPM2CNTH Bit 15 0x0062 TPM2CNTL Bit 7 0x0063 TPM2MODH Bit 15 0x0064 TPM2MODL Bit 7 0x0065 TPM2C0SC CH0F Freescale Semiconductor — — — — — — RXEDGIE 0 SBR12 SBR6 SBR5 SBR4 SCISWAI RSRC M TCIE RIE ILIE TC ...
Page 42
... RTCLKS RTIE RTCCNT RTCMOD — — — — — — MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ELS1B ELS1A — — — RTCPS — — — — — — Freescale Semiconductor Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — — ...
Page 43
... Reserved 0x183F — 0x1840 PTAPE PTAPE7 0x1841 PTASE PTASE7 0x1842 PTADS PTADS7 0x1843 Reserved — 0x1844 PTASC 0 Freescale Semiconductor 4-3, are accessed much less often than other I/O and control registers PIN COP ILOP COPT STOPE 0 COPW 0 ACIC — — ...
Page 44
... PTBPS1 PTBPS0 PTBES3 PTBES2 PTBES1 PTBES0 — — — PTCPE3 PTCPE2 PTCPE1 PTCPE0 PTCSE3 PTCSE2 PTCSE1 PTCSE0 PTCDS3 PTCDS2 PTCDS1 PTCDS0 GNGPS2 GNGPS1 GNGEN — — — — — — — — — Freescale Semiconductor Bit 0 — — — — — ...
Page 45
... FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC) to the unsecured state (1:0). Freescale Semiconductor Table 4-4, are located in the FLASH memory. These registers Table 4-4 ...
Page 46
... MC9S08SH32 Series usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX #RamLast+1 ...
Page 47
... Parameter Byte program Byte program (burst) Page erase Mass erase 1 Excluding start/end overhead Freescale Semiconductor (FCDIV)”). This register can be written only ) is used by the command processor to time FCLK = 1/f FCLK FCLK FCLK Table 4-5. Program and Erase Times ...
Page 48
... FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. 48 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 49
... The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. Freescale Semiconductor Note 1: Required only once after reset. WRITE TO FCDIV (Note 1) ...
Page 50
... WRITE COMMAND (0x25) TO FCMD WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles before TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) YES FPVIO OR FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...
Page 51
... For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of NVPROT) must Freescale Semiconductor NVPROT)”). Figure 4-4 ...
Page 52
... NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state disengages security and the other three combinations engage security. Notice the erased state (1:1) makes 52 1 A12 A11 A10 A9 A8 Figure 4-4. Block Protection Mechanism MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 53
... FLASH Registers and Control Bits The FLASH module has nine 8-bit registers in the high-page register space, two locations (NVOPT, NVPROT) in the nonvolatile register space in FLASH memory are copied into corresponding high-page Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 4 Memory ...
Page 54
... Refer to Table 4-3 and Table 4-4 refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.7.1 FLASH Clock Divider Register (FCDIV) Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time. ...
Page 55
... MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the background debug interface. SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. For more detailed information about security, refer to Freescale Semiconductor Table 4-7. FLASH Clock Divider Settings DIV f ...
Page 56
... Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. FLASH Protection Register (FPROT) 56 Table 4-9. Security States SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure KEYACC Description Section 4. (1) FPS MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY “Security.” Freescale Semiconductor (1) FPDIS ...
Page 57
... Protection Violation Flag — FPVIOL is set automatically when a command is written that attempts to erase or FPVIOL program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. Freescale Semiconductor Description 5 4 FPVIOL FACCERR ...
Page 58
... Execution,” for a detailed discussion of FLASH programming and FCMD Table 4-13. FLASH Commands FCMD Equate File Label 0x05 0x20 0x25 0x40 0x41 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Errors.” FACCERR is cleared by Table 4-13. Refer to Section mBlank mByteProg mBurstProg mPageErase mMassErase Freescale Semiconductor ...
Page 59
... Background debug forced reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Table 5-2) ...
Page 60
... LPO LPO MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY (SOPT1),” (SOPT2),” for additional COP Overflow Count COP is disabled cycles ( cycles (256 cycles (1.024 cycles 16 2 cycles 18 2 cycles Section A.12.1, “Control Timing,” for the Freescale Semiconductor ...
Page 61
... ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not recommended for anyone Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control MC9S08SH32 Series Data Sheet, Rev. 2 ...
Page 62
... INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY 0 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
Page 63
... The high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE ...
Page 64
... CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 — — LVWIE Low-voltage warning IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect — External pin — Illegal opcode — Illegal address Freescale Semiconductor ...
Page 65
... Table 4-3 assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “ ...
Page 66
... Section 5.5.2.2, “Edge and Level 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels IRQF IRQEDG IRQPE Description Sensitivity,” for more details. MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY IRQIE IRQMOD IRQACK Freescale Semiconductor ...
Page 67
... STOPE = 0 in the SOPT register. The BGND instruction is considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 5 4 ...
Page 68
... Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 68 Table 5-4. SRS Register Field Descriptions Description Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor BDFR 0 ...
Page 69
... POR reset. When configured as RESET, the pin will be unaffected by LVR or other internal resets. When RSTPE is set, an internal pullup device is enabled on RESET. 0 PTA5/IRQ/TCLK/RESET pin functions as PTA5, IRQ or TCLK. 1 PTA5/IRQ/TCLK/RESET pin functions as RESET. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 5 4 ...
Page 70
... TPM1CH0 Pin Select— This bit selects the location of the TPM1CH0 pin of the TPM1 module. T1CH0PS 0 TPM1CH0 on PTA0. 1 TPM1CH0 on PTC0 ACIC T2CH1PS 0 0 Table 5-7. SOPT2 Register Field Descriptions Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY T2CH0PS T1CH1PS Freescale Semiconductor 0 T1CH0PS 0 ...
Page 71
... Figure 5-8. System Device Identification Register — Low (SDIDL) Field 7:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08SH32 is hard coded to the value 0x01A. See also ID bits in Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 5 4 ID11 — ...
Page 72
... Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ADC and ACMP modules. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled LVWIE LVDRE LVDSE transitions below the trip point or after reset and V Supply Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY LVDE already below V Supply Freescale Semiconductor 0 BGBE 0 LVW ...
Page 73
... Partial Power Down Acknowledge — Writing PPDACK clears the PPDF bit PPDACK 0 Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected. PPDC 0 Stop3 mode enabled. 1 Stop2, partial power down, mode enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control PPDF 1 ...
Page 74
... Table 5-12. LVD and LVW trip point typical values LVDV:LVWV 0:0 0:1 1:0 1:1 1 See Electrical Characteristics appendix for minimum and maximum values. 74 LVW Trip Point V = 2.74 V LVW0 V = 2.92 V LVW1 V = 4.3 V LVW2 V = 4.6 V LVW3 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY 1 LVD Trip Point V = 2.56 V LVD0 V = 4.0 V LVD1 Freescale Semiconductor ...
Page 75
... In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. Freescale Semiconductor 2-1. The peripheral modules have priority over the general-purpose I/O NOTE Figure MC9S08SH32 Series Data Sheet, Rev ...
Page 76
... Because of this, the EMC emissions may be affected by enabling pins as high drive. 76 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
Page 77
... Ganged output on PTC3-PTC0 not available on 16-pin packages, however PTC0 control registers are still used to control ganged output. 2 When GNGEN = 1, PTC0 is forced to an output, regardless of the value in PTCDD0 in PTCDD. Freescale Semiconductor NOTE Table 2-1 for information on pin priority. Table 6-1. Ganged Output Pin Enable ...
Page 78
... The asserted status of a pin is reflected by its associated I/O general purpose data register. 78 Figure 6- CLR PORT INTERRUPT FF PTxMOD Figure 6-2. Pin Interrupt Block Diagram NOTE MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY BUSCLK PTxACK RESET PTxIF SYNCHRONIZER STOP BYPASS PTx STOP INTERRUPT REQUEST PTxIE Freescale Semiconductor ...
Page 79
... PPDACK bit in the SPMSC2 register. Access to I/O is now permitted again in the user application program. • In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 6 Parallel Input/Output Control 79 ...
Page 80
... Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and their pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. ...
Page 81
... Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. Freescale Semiconductor NOTE . DD level an external pullup should be used ...
Page 82
... PTADD5 PTADD4 PTADD3 0 0 Description PTAPE5 PTAPE4 PTAPE3 0 0 Table 6-4. PTAPE Register Field Descriptions Description NOTE MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY PTADD2 PTADD1 PTAPE2 PTAPE1 Freescale Semiconductor 0 PTADD0 0 0 PTAPE0 0 ...
Page 83
... PTA pin. For port A pins that are configured as inputs, these bits have no effect. PTADS 0 Low output drive strength selected for port A bit n. [7:6, 4:0] 1 High output drive strength selected for port A bit n. 5 Reserved Bits — These bits are unused on this MCU, writes have no affect and could read 0s. Reserved Freescale Semiconductor PTASE4 PTASE3 0 ...
Page 84
... Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin. PTAPS[3:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt PTAIF Description PTAPS3 Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY PTAIE PTAMOD PTAACK PTAPS2 PTAPS1 PTAPS0 Freescale Semiconductor ...
Page 85
... Port A Edge Selects — Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active PTAES[3:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. Freescale Semiconductor ...
Page 86
... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn PTBD5 PTBD4 PTBD3 Figure 6-11. Port B Data Register (PTBD) Description PTBDD5 PTBDD4 PTBDD3 Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY PTBD2 PTBD1 PTBD0 PTBDD2 PTBDD1 PTBDD0 Freescale Semiconductor ...
Page 87
... Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control PTBSE[7:0] is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. Freescale Semiconductor PTBPE5 ...
Page 88
... Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B PTBMOD interrupt pins. 0 Port B pins detect edges only. 1 Port B pins detect both edges and levels PTBDS5 PTBDS4 PTBDS3 Description PTBIF Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY PTBDS2 PTBDS1 PTBDS0 PTBIE PTBMOD PTBACK Freescale Semiconductor ...
Page 89
... Port B Edge Selects — Each of the PTBESn bits serves a dual purpose by selecting the polarity of the active PTBES[3:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. Freescale Semiconductor ...
Page 90
... Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn PTCD5 PTCD4 PTCD3 Figure 6-19. Port C Data Register (PTCD) Description PTCDD5 PTCDD4 PTCDD3 Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY PTCD2 PTCD1 PTCD0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 91
... Output Slew Rate Enable for Port C Bits — Each of these control bits determines if the output slew rate control PTCSE[7:0] is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. Freescale Semiconductor PTCPE5 ...
Page 92
... Ganged Output Drive Enable Bit— This write-once control bit selects whether the ganged output drive feature GNGEN is enabled. 0 Ganged output drive disabled. 1 Ganged output drive enabled. PTC0 forced to output regardless of the value of PTCDD0 in PTCDD PTCDS5 PTCDS4 PTCDS3 Description GNGPS5 GNGPS4 GNGPS3 Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY PTCDS2 PTCDS1 PTCDS0 GNGPS2 GNGPS1 GNGEN Freescale Semiconductor ...
Page 93
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...
Page 94
... For compatibility with the earlier M68HC05 Family forced to 0x00 during reset. Reset has no effect on the contents ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 95
... Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. ...
Page 96
... No carry out of bit 7 1 Carry out of bit CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 97
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 98
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 98 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 99
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08SH32 Series Data Sheet, Rev. 2 ...
Page 100
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 100 chapter for more details. MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 101
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 102
... E4 ff rpp 3 F4 rfp pprpp 4 ff prpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 78 rfwp 6 ff prfwpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 77 rfwp 6 ff prfwpp Freescale Semiconductor Affect on CCR ...
Page 103
... Branch if Lower or Same ( Branch if Less Than (if N ⊕ (Signed) BLT rel BMC rel Branch if Interrupt Mask Clear ( BMI rel Branch if Minus ( BMS rel Branch if Interrupt Mask Set ( BNE rel Branch if Not Equal ( Freescale Semiconductor Object Code REL 24 rr DIR (b0 DIR (b1 DIR (b2) ...
Page 104
... Freescale Semiconductor ...
Page 105
... DEC oprx8,SP Divide DIV A ← (H:A)÷(X); H ← Remainder EOR #opr8i Exclusive OR Memory with Accumulator A ← (A ⊕ M) EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP Freescale Semiconductor Object Code IMM A1 DIR B1 EXT C1 IX2 D1 IX1 SP2 ...
Page 106
... prpp – – ↕ ↕ – rpp 3 FE rfp pprpp 4 ff prpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 78 rfwp 6 ff prfwpp rfwpp ↕ – – 0 ↕ ↕ rfwpp 4 74 rfwp 6 ff prfwpp Freescale Semiconductor Affect on CCR ...
Page 107
... Rotate Left through Carry ROLA ROLX C ROL oprx8,X b7 ROL ,X ROL oprx8,SP ROR opr8a Rotate Right through Carry RORA RORX ROR oprx8 ROR ,X ROR oprx8,SP Freescale Semiconductor Object Code DIR/DIR 4E DIR/IX+ 5E IMM/DIR 6E IX+/DIR 7E INH 42 M ← – (M) = $00 – (M) DIR 30 INH 40 X ← ...
Page 108
... Freescale Semiconductor ...
Page 109
... A ← (CCR) TST opr8a Test for Negative or Zero TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Transfer SP to Index Reg. TSX H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA A ← (X) Freescale Semiconductor Object Code IMM A0 ii DIR B0 dd EXT IX2 IX1 ...
Page 110
... Read vector from $FFxx (high byte first) v Write 8-bit operand w CCR Effects: ↕ Set or cleared – Not affected U Undefined MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Affect Cyc-by-Cyc on CCR Details – – – – – – – – 0 – – – fp... Freescale Semiconductor ...
Page 111
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 112
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 113
... The ACMP module can be configured to connect the output of the analog comparator to TPM1 input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPM1CH0 pin is not available externally regardless of the configuration of the TPM1 module for channel 0. Freescale Semiconductor Section 5.7.6, “System Power Management Status and Control 1 Section A.6, “DC MC9S08SH32 Series Data Sheet, Rev ...
Page 114
... PTA2/PIA2/SD/ADP2 SDA PTA1/PIA1/TPM2CH0/ADP1/ACMP– SS PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD PTB5/TPM1CH1/SS TCLK PTB4/TPM2CH1/MISO TPM1CH0 PTB3/PIB3/MOSI/ADP7 TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 and V respectively Freescale Semiconductor ...
Page 115
... ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. 8.4 Block Diagram The block diagram for the Analog Comparator module is shown Freescale Semiconductor Figure MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 8 Analog Comparator (S08ACMPV3) 8-2 ...
Page 116
... Chapter 8 Analog Comparator (S08ACMPV3) Internal Reference ACMP+ ACMP- Figure 8-2. Analog Comparator 5V (ACMP5) Block Diagram 116 Internal Bus ACBGS Status & Control ACME Register + Interrupt Control - Comparator MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ACMP INTERRUPT REQUEST ACIE ACF ACOPE ACMPO Freescale Semiconductor ...
Page 117
... Refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all ACMP registers.This section refers to registers and control bits only by their names . Some MCUs may have more than one ACMP, so register names include placeholder characters to identify which ACMP is being referenced. Freescale Semiconductor Table 8-1. Table 8-1. Signal Properties Function Inverting analog input to the ACMP ...
Page 118
... ACMOD 00 Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge 118 ACO ACF ACIE Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ACOPE ACMOD Freescale Semiconductor ...
Page 119
... The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPO pin using ACOPE. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 120
... Chapter 8 Analog Comparator (S08ACMPV3) 120 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 121
... PTC3/ADP11 01100 AD12 PTC4/ADP12 01101 AD13 PTC5/ADP13 01110 AD14 PTC6/ADP14 01111 AD15 PTC7/ADP15 1 For information, see Section 9.1.5, “Temperature Freescale Semiconductor NOTE Table 9-1. ADC Channel Assignment Input ADCH PTA0/AD0 PTA1/ADP1 PTA2/ADP2 PTA3/ADP3 PTB0/ADP4 PTB1/ADP5 PTB2/ADP6 PTB3/ADP7 PTC0/ADP8 PTC1/ADP9 Sensor”. ...
Page 122
... V ) after being divided down from the ALTCLK input as ADCK . For value of bandgap voltage, see DD , convert the digital value of AD26 into a voltage, DD MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY (SPMSC1)”. and V , respectively. DDA SSA Section A.6, “DC V TEMP Freescale Semiconductor ...
Page 123
... In application code, the user would then calculate the temperature using temperature is above or below 25°C. Once determined if the temperature is above or below 25°C, the user can recalculate the temperature using the hot or cold slope value obtained during calibration. Freescale Semiconductor ) ÷ m) Temp = 25 - ((V -V ...
Page 124
... PTA2/PIA2/SD/ADP2 SDA PTA1/PIA1/TPM2CH0/ADP1/ACMP– SS PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD PTB5/TPM1CH1/SS TCLK PTB4/TPM2CH1/MISO TPM1CH0 PTB3/PIB3/MOSI/ADP7 TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 and V respectively Freescale Semiconductor ...
Page 125
... Selectable asynchronous hardware conversion trigger. • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 9.1.7 Block Diagram Figure 9-2 provides a block diagram of the ADC module Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY 125 ...
Page 126
... Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL Analog power supply V DDAD V Analog ground SSAD MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Async Clock Gen ADACK Bus Clock ÷2 ALTCLK 1 AIEN Interrupt 2 COCO 3 Freescale Semiconductor ...
Page 127
... Status and Control Register 1 (ADCSC1) This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). Freescale Semiconductor ) DDAD as its power connection. In some packages, V ...
Page 128
... Figure 9-4. Input Channel Select Input Select AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ADCH ADCH Input Select 10000 AD16 10001 AD17 10010 AD18 10011 AD19 10100 AD20 10101 AD21 10110 AD22 10111 AD23 Freescale Semiconductor ...
Page 129
... Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Input Select AD8 AD9 ...
Page 130
... In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data in ADCRL becomes invalid. 130 Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ADR9 ADR8 Freescale Semiconductor ...
Page 131
... ADCV6 W Reset Figure 9-9. Compare Value Low Register(ADCCVL) 9.3.7 Configuration Register (ADCCFG) ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power or long sample time. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1 ADR5 ADR4 ADR3 0 0 ...
Page 132
... Divide Ratio Table 9-7. Conversion Modes Mode Description 8-bit conversion (N=8) Reserved 10-bit conversion (N=10) Reserved MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY MODE ADICLK Table Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Freescale Semiconductor 9-7. ...
Page 133
... ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-8. Input Clock Select Selected Clock Source Bus clock Bus clock divided by 2 ...
Page 134
... ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled 134 Description ADPC13 ADPC12 ADPC11 Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ADPC10 ADPC9 ADPC8 Freescale Semiconductor ...
Page 135
... AD19 pin I/O control enabled 1 AD19 pin I/O control disabled 2 ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Description ADPC21 ...
Page 136
... Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC will not perform according to specifications. If the available clocks 136 Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 137
... In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SH32 Series Data Sheet, Rev. 2 ...
Page 138
... ADLSMP is used to select between short and long sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. The 138 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ). After f ADCK Freescale Semiconductor ...
Page 139
... MHz, then the conversion time for a single conversion is: Conversion time = Number of bus cycles = 3.5 μ MHz = 28 cycles The ADCK frequency must be between f maximum to meet ADC specifications. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) frequency, precise sample time for continuous conversions ADCK ADICLK ...
Page 140
... If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. 140 NOTE MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 141
... Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) NOTE Conversions) is cleared when entering stop3 ...
Page 142
... Software trigger selected Compare function disabled Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) MC9S08SH32 Series Data Sheet, Rev ...
Page 143
... When available on a separate pin, both V as their corresponding MCU digital supply (V noise immunity and bypass capacitors placed as near as possible to the package. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ...
Page 144
... PRELIMINARY on some devices. The low DDAD on some devices may be DDAD spec and the V potential (V DDAD must be connected to the same REFL . Setting the pin control register bits for and the input is equal to or REFL , the converter circuit converts it REFL Freescale Semiconductor REFH ...
Page 145
... I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: Place a 0.01 μF capacitor (C • improve noise issues but will affect sample rate based on the external analog source resistance). Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) lower than ...
Page 146
... Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the 146 LSB REFH REFL ). Note, if the last conversion is $3FE, then the LSB MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY , one-time error. LSB Eqn. 9-2 . LSB ). Note, if the first LSB LSB ) is used. LSB Freescale Semiconductor ) is ...
Page 147
... Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) and will increase with noise. This error may be LSB MC9S08SH32 Series Data Sheet, Rev ...
Page 148
... Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 148 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 149
... IICPS in SOPT1 selects which general-purpose I/O ports are associated with IIC operation. IICPS in SOPT1 0 (default) 1 Figure 10-1 shows the MC9S08SH32 Series block diagram with the IIC module highlighted. Freescale Semiconductor NOTE Table 10-1. IIC Position Options Port Pin for SDA ...
Page 150
... PTA2/PIA2/SDA/ADP2 SDA PTA1/PIA1/TPM2CH0/ADP1/ACMP– SS PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD PTB5/TPM1CH1/SS TCLK PTB4/TPM2CH1/MISO TPM1CH0 PTB3/PIB3/MOSI/ADP7 TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 and V respectively Freescale Semiconductor ...
Page 151
... Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 10 Inter-Integrated Circuit (S08IICV2) ...
Page 152
... This section consists of the IIC register descriptions in address order. 152 FREQ_REG ADDR_REG STATUS_REG Start Stop Arbitration Control SCL SDA Figure 10-2. IIC Functional Block Diagram MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Data Bus Interrupt DATA_MUX DATA_REG In/Out Data Shift Register Address Compare Freescale Semiconductor ...
Page 153
... Refer to the direct-page register summary in the assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 10.3.1 IIC Address Register (IICA AD7 AD6 ...
Page 154
... MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY × SDA hold value × SCL Start hold value × SCL Stop hold value SCL Start SCL Stop 3.000 5.500 4.000 5.250 4.000 5.250 4.250 5.125 4.750 5.125 Freescale Semiconductor Eqn. 10-1 Eqn. 10-2 Eqn. 10-3 Eqn. 10-4 ...
Page 155
... SCL SDA Hold (Start) (hex) Divider Value Value 104 21 17 128 112 17 1B 128 17 1C 144 25 1D 160 25 1E 192 33 1F 240 33 Freescale Semiconductor Table 10-5. IIC Divider and Hold Values SDA Hold ICR (Stop) (hex) Value 118 121 3F MC9S08SH32 Series Data Sheet, Rev. 2 ...
Page 156
... Repeat start. Writing this bit generates a repeated start condition provided it is the current master. This RSTA bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. 156 MST TX TXAK Figure 10-5. IIC Control Register (IICC1) Table 10-6. IICC1 Field Descriptions Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY RSTA Freescale Semiconductor ...
Page 157
... Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after RXAK the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received Freescale Semiconductor BUSY 0 ARBL ...
Page 158
... IIC Control Register 2 (IICC2 GCAEN ADEXT W Reset Unimplemented or Reserved 158 DATA Figure 10-7. IIC Data I/O Register (IICD) Table 10-8. IICD Field Descriptions Description NOTE Figure 10-8. IIC Control Register (IICC2) MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY AD10 AD9 AD8 Freescale Semiconductor ...
Page 159
... Stop signal The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Freescale Semiconductor Table 10-9. IICC2 Field Descriptions Description Figure MC9S08SH32 Series Data Sheet, Rev. 2 ...
Page 160
... Bit Start Write Signal Figure 10-9. IIC Bus Transmission Signals MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY lsb Data Byte No Ack Signal Bit lsb New Calling Address No Read/ Ack Write Bit Figure 10-9, a start signal is Figure 10-9). Freescale Semiconductor Stop Stop Signal ...
Page 161
... The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, Freescale Semiconductor 10-9. There is one clock pulse on SCL for each data bit, the msb being MC9S08SH32 Series Data Sheet, Rev ...
Page 162
... SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 162 Delay Figure 10-10. IIC Clock Synchronization MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Figure 10-10). When all Start Counting High Period Freescale Semiconductor ...
Page 163
... After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. Freescale Semiconductor Table 10-10). When a 10-bit address follows a start condition, ...
Page 164
... ARBL bit in the status register is set. 164 Table 10-12 Table 10-12. Interrupt Summary Status TCF IAAS ARBL MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY occur, provided the IICIE bit Flag Local Enable IICIF IICIE IICIF IICIE IICIF IICIE Freescale Semiconductor ...
Page 165
... A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing it. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 10 Inter-Integrated Circuit (S08IICV2) 165 ...
Page 166
... IIC operations. For slave operation, an Register Model AD[7:1] ICR MST TX TXAK RSTA BUSY ARBL 0 SRW DATA 0 0 AD10 0 Figure 10-11. IIC Module Quick Start MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY IICIF RXAK AD9 AD8 Freescale Semiconductor ...
Page 167
... When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Freescale Semiconductor Clear IICIF ...
Page 168
... Chapter 10 Inter-Integrated Circuit (S08IICV2) 168 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 169
... When the internal reference is enabled in stop mode (IREFSTEN = 1), the voltage regulator must also be enabled in stop mode by setting the LVDE and LVDSE bits in the SPMSC1 register. Figure 11-1 shows the MC9S08SH32 block diagram with the ICS highlighted. Freescale Semiconductor NOTE for a detailed view of the MC9S08SH32 Series Data Sheet, Rev. 2 ...
Page 170
... PTA2/PIA2/SD/ADP2 SDA PTA1/PIA1/TPM2CH0/ADP1/ACMP– SS PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD PTB5/TPM1CH1/SS TCLK PTB4/TPM2CH1/MISO TPM1CH0 PTB3/PIB3/MOSI/ADP7 TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 and V respectively Freescale Semiconductor ...
Page 171
... Control signals for a low power oscillator as the external reference clock are provided — HGO, RANGE, EREFS, ERCLKEN, EREFSTEN • FLL Engaged Internal mode is automatically selected out of reset 11.1.3 Block Diagram Figure 11-2 is the ICS block diagram. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 11 Internal Clock Source (S08ICSV2) 171 ...
Page 172
... FLL. 172 Block ERCLKEN EREFS EREFSTEN IRCLKEN IREFSTEN CLKS Internal LP Reference Clock DCOOUT 9 DCO TRIM 9 n RDIV_CLK Filter FLL Internal Clock Source Block l (FEI) (FEE) l (FBI) MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ICSERCLK ICSIRCLK BDIV ICSOUT n=0-3 ICSLCLK / 2 ICSFFCLK Freescale Semiconductor ...
Page 173
... Figure 11 summary of ICS registers. Name 7 R ICSC1 CLKS W R ICSC2 BDIV W R ICSTRM ICSSC W Freescale Semiconductor l Low Power (FBILP) l (FBE) l Low Power (FBELP) Table 11-1. ICS Register Summary RDIV RANGE HGO LP TRIM 0 0 IREFST MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 11 Internal Clock Source (S08ICSV2) ...
Page 174
... Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before entering stop 0 Internal reference clock is disabled in stop 174 5 4 RDIV 0 0 Figure 11-3. ICS Control Register 1 (ICSC1) Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY IREFS IRCLKEN IREFSTEN Freescale Semiconductor 0 0 ...
Page 175
... External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock EREFSTEN remains enabled when the ICS enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop Freescale Semiconductor 5 4 RANGE HGO 0 0 Figure 11-4 ...
Page 176
... CLKS bits due to internal synchronization between clock domains. 00 Output of FLL is selected. 01 FLL Bypassed, Internal reference clock is selected. 10 FLL Bypassed, External reference clock is selected. 11 Reserved. 176 TRIM Figure 11-5. ICS Trim Register (ICSTRM) Description IREFST Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY CLKST OSCINIT FTRIM Freescale Semiconductor ...
Page 177
... The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the allowed movements between the states. 11.4.1.1 FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: Freescale Semiconductor Description IREFS=1 CLKS=00 FLL Engaged Internal (FEI) ...
Page 178
... In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal reference clock is enabled. 178 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 179
... After a change in the IREFS value the FLL will begin locking again after a few full cycles of the resulting divided reference frequency. The completion of the switch is shown by the IREFST bit. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 180
... FLL and will only be used as ICSERCLK. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support (see the Overview chapter). 180 chapter). MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Device Freescale Semiconductor ...
Page 181
... BDIV=00 (divide by 1), RDIV ≥ 010 • BDIV=01 (divide by 2), RDIV ≥ 011 • BDIV=10 (divide by 4), RDIV ≥ 100 • BDIV=11 (divide by 8), RDIV ≥ 101 • Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 11 Internal Clock Source (S08ICSV2) 181 ...
Page 182
... Chapter 11 Internal Clock Source (S08ICSV2) 182 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 183
... The external clock for the MTIM module, TCLK, is selected by setting CLKS = 1:1 or 1:0 in MTIMCLK, which selects the TCLK pin input. The TCLK input can be enabled as external clock inputs to both the MTIM and TPM modules simultaneously. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 184
... PTA2/PIA2/SD/ADP2 SDA PTA1/PIA1/TPM2CH0/ADP1/ACMP– SS PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD PTB5/TPM1CH1/SS TCLK PTB4/TPM2CH1/MISO TPM1CH0 PTB3/PIB3/MOSI/ADP7 TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 and V respectively Freescale Semiconductor ...
Page 185
... The MTIM suspends all counting until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written MTIMMOD written). Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Chapter 12 Modulo Timer (S08MTIMV1) ...
Page 186
... DIVIDE BY SELECT PS CLKS Table 12-1. Signal Properties Function External clock source input into MTIM MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY 12-2. 8-BIT COUNTER (MTIMCNT) 8-BIT COMPARATOR 8-BIT MODULO (MTIMMOD) Table 12-1. I/O I Pins and Connections chapter for Freescale Semiconductor TRST TSTP ...
Page 187
... Refer to the direct-page register summary in the assignments for all MTIM registers.This section refers to registers and control bits only by their names and relative address offsets. Some MCUs may have more than one MTIM, so register names include placeholder characters to identify which MTIM is being referenced. Freescale Semiconductor TOF ...
Page 188
... MTIM Counter Stop — When set, this read/write bit stops the MTIM counter at its current value. Counting resumes TSTP from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. 0 MTIM counter is active. 1 MTIM counter is stopped. 3:0 Unused register bits, always read 0. 188 TSTP TRST Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 189
... Encoding 4. MTIM clock source ÷ 16 0101 Encoding 5. MTIM clock source ÷ 32 0110 Encoding 6. MTIM clock source ÷ 64 0111 Encoding 7. MTIM clock source ÷ 128 1000 Encoding 8. MTIM clock source ÷ 256 All other encodings default to MTIM clock source ÷ 256. Freescale Semiconductor CLKS 0 ...
Page 190
... MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to $00 and clears TOF. Reset sets the modulo to $00. 190 COUNT Figure 12-6. MTIM Counter Register Description MOD Figure 12-7. MTIM Modulo Register Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 191
... The MTIM allows for an optional interrupt to be generated whenever TOF is set. To enable the MTIM overflow interrupt, set the MTIM overflow interrupt enable bit (TOIE) in MTIMSC. TOIE should never be written while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 192
... When the counter, MTIMCNT, reaches the modulo value of $AA, the counter overflows to $00 and continues counting. The timer overflow flag, TOF, sets when the counter value changes from $AA to $00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. 192 $A8 $A9 $AA $AA MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY $00 $01 Freescale Semiconductor ...
Page 193
... This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake up from low power modes without the need of external components. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 194
... PTA2/PIA2/SD/ADP2 SDA PTA1/PIA1/TPM2CH0/ADP1/ACMP– SS PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD PTB5/TPM1CH1/SS TCLK PTB4/TPM2CH1/MISO TPM1CH0 PTB3/PIB3/MOSI/ADP7 TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 PTC3/ADP11 PTC2/ADP10 PTC1/TPM1CH1/ADP9 PTC0/TPM1CH0/ADP8 and V respectively Freescale Semiconductor ...
Page 195
... The RTC suspends all counting during active background mode until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as the RTCMOD register is not written and the RTCPS and RTCLKS bits are not altered. Freescale Semiconductor MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY ...
Page 196
... Figure 13-2. 8-Bit Modulo (RTCMOD) 8-Bit Comparator RTC 8-Bit Counter Clock (RTCCNT) Table 13-1. RTC Register Summary RTIF RTCLKS RTIE MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY RTIF E R RTIE Write 1 to RTIF RTCPS RTCCNT RTCMOD Freescale Semiconductor RTC Interrupt Request 0 ...
Page 197
... See counters. Reset clears RTCPS. RTCLKS[ Off Off Freescale Semiconductor 5 4 RTCLKS RTIE 0 0 Table 13-2. RTCSC Field Descriptions Description Table 13-3. Changing the prescaler value clears the prescaler and RTCCNT Table 13-3. RTC Prescaler Divide-by values RTCPS ...
Page 198
... The RTC clock select bits (RTCLKS) select the desired clock source different value is written to RTCLKS, the prescaler and RTCCNT counters are reset to 0x00. 198 RTCCNT Table 13-4. RTCCNT Field Descriptions Description RTCMOD Table 13-5. RTCMOD Field Descriptions Description MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY Freescale Semiconductor ...
Page 199
... RTCSC. RTIF is cleared by writing RTIF. 13.4.1 RTC Operation Example This section shows an example of the RTC operation as the counter reaches a matching value from the modulo register. Freescale Semiconductor Table 13-6 shows different prescaler period values. Table 13-6. Prescaler Period 1-MHz External Clock ...
Page 200
... Minutes = 0; Hours = 0; Days=0; /* Configure RTC to interrupt every 1 second from 1-kHz clock source */ RTCMOD.byte = 0x00; RTCSC.byte = 0x1F; /********************************************************************** Function Name : RTC_ISR Notes : Interrupt service routine for RTC module. **********************************************************************/ 200 0x53 0x54 0x55 0x55 MC9S08SH32 Series Data Sheet, Rev. 2 PRELIMINARY 0x00 0x01 Freescale Semiconductor ...