MC9S08SH16CTL Freescale, MC9S08SH16CTL Datasheet - Page 22

• Manufacturer Part Number: MC9S08SH16CTL
• Manufacturer: Freescale

Specifications of MC9S08SH16CTL

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

EXTAL
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one half
of the bus clock frequency.
Chapter 1 Device Overview
1.3
Figure 1-2
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function.
The following defines the clocks used in this MCU:
22
XOSC
1 kHZ
LPO
ICS
•
•
•
•
•
•
•
•
XTAL
BUSCLK — The frequency of the bus is always half of ICSOUT.
ICSOUT — Primary output of the ICS and is twice the bus frequency.
ICSLCLK — Development tools can select this clock source to speed up BDC communications in
systems where the bus clock is configured to run at a very slow frequency.
ICSERCLK — External reference clock can be selected as the RTC clock source and as the
alternate clock for the ADC module.
ICSIRCLK — Internal reference clock can be selected as the RTC clock source.
ICSFFCLK — Fixed frequency clock can be selected as clock source for the TPM1, TPM2 and
MTIM modules.
LPOCLK — Independent 1-kHz clock source that can be selected as the clock source for the COP
and RTC modules.
TCLK — External input clock source for TPM1, TPM2 and MTIM and is referenced as TPMCLK
in TPM chapters.
System Clock Distribution
LPOCLK
ICSERCLK
ICSIRCLK
ICSFFCLK
ICSOUT
ICSLCLK
shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
CPU
÷
÷
2
2
BUSCLK
Figure 1-2. System Clock Distribution Diagram
RTC
SYNC*
MC9S08SH32 Series Data Sheet, Rev. 2
COP
TCLK
BDC
TPM1
PRELIMINARY
FFCLK*
TPM2
ADC has min and max
frequency requirements.
See the ADC chapter
and electricals appendix
for details.
MTIM
ADC
SCI
IIC
SPI
Freescale Semiconductor
FLASH has frequency
requirements for program
and erase operation. See
the electricals appendix
for details.
FLASH