MC9S08SH16CTL Freescale, MC9S08SH16CTL Datasheet - Page 68

no-image

MC9S08SH16CTL

Manufacturer Part Number
MC9S08SH16CTL
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S08SH16CTL

Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
SCI/SPI
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
16-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
TSSOP
Program Memory Type
Flash
Program Memory Size
16KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08SH16CTL
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MC9S08SH16CTL
Manufacturer:
FREESCALE
Quantity:
5 000
Part Number:
MC9S08SH16CTL
Manufacturer:
FREESCALE
Quantity:
5 000
1
Chapter 5 Resets, Interrupts, and General System Control
5.7.3
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
68
BDFR is writable only through serial background debug commands, not from user programs.
Reset:
BDFR
Field
Field
ILAD
LVD
3
1
0
W
R
System Background Debug Force Reset Register (SBDFR)
Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address
1 Reset caused by an illegal address
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
0
0
7
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
0
0
6
Table 5-5. SBDFR Register Field Descriptions
Table 5-4. SRS Register Field Descriptions
MC9S08SH32 Series Data Sheet, Rev. 2
0
0
5
PRELIMINARY
0
0
4
Description
Description
3
0
0
0
0
2
Freescale Semiconductor
0
0
1
BDFR
0
0
0
1

Related parts for MC9S08SH16CTL