SC1200UFH-266BF 33 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266BF 33 Datasheet - Page 160

• Manufacturer Part Number: SC1200UFH-266BF 33
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266BF 33

• Lead Free Status / RoHS Status: Compliant

6.2.9.3
The SC1200/SC1201 processor supports up to three
power planes. Three signals are used to control these
power planes. Table 6-6 describes the signals and when
each is asserted.
These signals allow control of the power of system devices
and the SC1200/SC1201 processor itself. Table 6-7
describes the SC1200/SC1201 processor’s power planes
with respect to the different Sleep and Global states.
The SC1200/SC1201 processor’s power planes are con-
trolled externally by the three signals (i.e., the system
designer should make sure the system design is such that
Table 6-7 is met) for all supported Sleep states.
V
exists as long as the AC power is plugged in (for desktop
systems) or the main battery is charged (for mobile sys-
tems). V
The case in which V
Off (G3).
160
Table 6-7. Power Planes vs. Sleep/Global States
Sleep/
Global
State
S0, SL1 and
SL2
SL3, SL4
and SL5
G3
No Power
Illegal
Signal
PWRCNT1
PWRCNT2
ONCTL#
SB
Table 6-6. Power Planes Control Signals vs.
and V
BAT
Power Planes Control
BAT
exists as long as the RTC battery is charged.
are not controlled by any control signal. V
AV
V
CCCRT
AV
S0
CCTV,
V
1
1
0
SB
CORE
CCCRT
On
Off
Off
Off
On
Sleep States
32579B
does not exist is called Mechanical
, V
V
PLL
,
SL1
I/O
1
1
0
,
,
V
SB
SL2
0
1
0
On
On
Off
Off
Off
, V
SBL
SL3
0
0
0
On or Off
On or Off
On or Off
V
On
Off
BAT
SL4
SL5
and
0
0
1
SB
6.2.9.4
The SC1200/SC1201 processor supports power manage-
ment events that can manage:
• Transition of the system from a Sleep state to a Work
• Enabled wakeup events to set the WAK_STS bit
• Generation of an interrupt. This invokes the relevant
Table 6-8 lists the power management events that can gen-
erate an SCI or SMI.
Event
Power Button
Power Button Override
Bus Master Request
Thermal Monitoring
USB
RTC
ACPI Timer
GPIO
SDATA_IN2 (AC97)
IRRX1
RI2#
GPWIO
Internal SMI signal
state. This is done by the hardware. These events are
defined as wakeup events.
(F1BAR1+I/O Offset 08h[15]) to 1, when transitioning
the system back to the working state.
software driver. The interrupt can either be an SMI or
SCI (selected by the SCI_EN bit, F1BAR1+I/O Offset
0Ch[0]). These events are defined as interrupt events.
Table 6-8. Power Management Events
AMD Geode™ SC1200/SC1201 Processor Data Book
Power Management Events
SCI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Core Logic Module
SMI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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