5962-9314402MUA QP SEMICONDUCTOR, 5962-9314402MUA Datasheet - Page 12

• Manufacturer Part Number: 5962-9314402MUA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-9314402MUA

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DSCC FORM 2234
APR 97
8/
9/
10/ This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay
11/ This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal
12/ If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed.
13/ This specification is a measure of the delay associated with the internal register feedback path. This is the delay from
14/ This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine
15/ This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can
16/ This frequency indicates the maximum frequency at which the device may operate in data path mode. This delay assumes
17/ This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or
18/ This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is
19/ This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register
20/ This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t
21/ This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to
22/ This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine
23/ This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with
24/ This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode.
25/ This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be
26/ This parameter indicates the minimum time that the previous register output data is maintained on the output after an
This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay
assumes no expander terms are used to form the logic function.
This specification is a measure of the delay from an input signal applied to a dedicated input to combinatorial output on any
output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander
logic delay for one pass through the expander logic.
assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass
through the expander logic.
to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register
is synchronously clocked and all feedback is within the same LAB.
These parameters are t
synchronous clock to LAB logic array input. This delay plus the register set-up time, t
an internal synchronous state machine configuration. This delay is for feedback within the same LAB.
configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to
dedicated inputs. All feedback is assumed to be local, originating within the same LAB.
operate. If register output states must also control external points, this frequency can still be observed as long as this
frequency is less than 1/t
data input signals are applied to dedicated inputs and no expander logic is used. If any of the data inputs are I/O pins, t
at he appropriate t
buried register can be cycled by a clock signal applied to the dedicated clock input pin.
maintained on the output pin.
output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are
used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to a dedicated input
pin and all feedback is within a single LAB.
t
polarity, t
LAB logic array input. This delay plus the asynchronous register set-up time, t
internal asynchronous clocked state machine configuration. This delay is for feedback within the same LAB, assumes no
expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin.
configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are
applied to dedicated inputs, and that no expander logic is employed in the clock signal path or data path.
internal-only feedback can operate. This parameter is determined by the lesser of (1/(t
register output states must also control external points, this frequency can still be observed as long as this frequency is less
than 1/t
This specification is determined by the least of 1/(t
signals are applied to dedicated input pins and no expander logic is used.
cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin.
asynchronous register clock input applied to an external dedicated input pin.
AWL
DEFENSE SUPPLY CENTER COLUMBUS
parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative
ACO1
MICROCIRCUIT DRAWING
AWH
COLUMBUS, OHIO 43218-3990
.
should be used for both t
STANDARD
S
for calculation.
S2
CO1
for synchronous operation and t
.
TABLE I. Electrical performance characteristics - Continued.
AWH
and t
AWL
AWH
.
+ t
AWL
AS2
),1/(t
for asynchronous operation.
AS1
SIZE
A
+ t
AH
) or 1/t
AS1
REVISION LEVEL
ACO1
, is the minimum internal period for an
. It assumes data and clock input
S1
ACF
, is the minimum internal period for
B
+ 1/t
AS1
)) or (1/(t
SHEET
AWH
5962-93144
+ t
AWL
AWH
)). If
12
and
S2
is