5962-9314402MUA QP SEMICONDUCTOR, 5962-9314402MUA Datasheet - Page 21

• Manufacturer Part Number: 5962-9314402MUA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-9314402MUA

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DSCC FORM 2234
APR 97
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
4.2.2 Additional criteria for device classes Q and V.
a.
b.
c.
d.
e.
a.
(1)
Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical
Prior to burn-in, the devices shall be programmed (see 4.5 herein) with a checkerboard pattern or equivalent
The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
Interim and final electrical test parameters shall be as specified in table IIA herein.
A data retention stress test shall be included as part of the screening procedure and shall consist of the following steps:
Margin test method. (Steps 1 through 4 may be performed at wafer level.)
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
DEFENSE SUPPLY CENTER COLUMBUS
parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
(manufacturers at their option may employ an equivalent pattern provided it is a topologically true alternating bit
pattern). The pattern shall be read before and after burn-in. Devices having bits not in the proper state after burn-in
shall constitute a device failure and shall be included in the PDA calculation and shall be removed from the lot. The
manufacturer as an option may use built-in test circuitry by testing the entire lot to verify programmability and AC
performance without programming the user array.
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(a) Static burn-in for device class M (method 1015 of MIL-STD-883, test condition C; for circuit, see 4.2.1c herein) may
storage temperature shall not exceed +200°C for packaged devices or +300°C for unassmbled devices.) If steps 1
through 4 are not done at wafer level, then a sample of 116 devices shall be selected to accomplish this test with the
pass criteria of no failures.
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(Steps 1 through 4 may be performed at the wafer level. Failures shall be removed from the lot. The maximum
(1) Program a minimum or 95 percent of the total number of cells, including the slowest programming cell
(2) Bake, unbiased, for 72 hours at +140°C or for 32 hours at +150°C or for 8 hours at +200°C or for 2 hours at
(3) Perform electrical test (see 4.2.1b) at +25°C including a margin test at Vm = +5.7 V and loose timing (i.e., 1 µs).
(4) Erase (see 3.11.1).
(5) Verify erasure (see 3.11.3).
Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).
MICROCIRCUIT DRAWING
be done in lieu of dynamic burn-in.
COLUMBUS, OHIO 43218-3990
(see 3.11.2).
+300°C for unassembled devices only.
STANDARD
SIZE
A
REVISION LEVEL
B
SHEET
5962-93144
21