82V3380PFG IDT, Integrated Device Technology Inc, 82V3380PFG Datasheet - Page 47
82V3380PFG
Manufacturer Part Number
82V3380PFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3380PFG.pdf
(175 pages)
Specifications of 82V3380PFG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Table 32: Related Bit / Register in Chapter 3.15
3.15
interrupt status bit. If the corresponding interrupt enable bit is set, any of
the interrupts can be reported by the INT_REQ pin. The output charac-
teristics on the INT_REQ pin are determined by the HZ_EN bit and the
INT_POL bit.
interrupt status bit. The INT_REQ pin will be inactive only when all the
pending enabled interrupts are cleared.
reported by the TDO pin, as determined by the LOS_FLAG_TO_TDO
bit.
Functional Description
IDT82V3380
The interrupt sources of the device are as follows:
All of the above interrupt events are indicated by the corresponding
Interrupt events are cleared by writing a ‘1’ to the corresponding
In addition, the interrupt of T0 selected input clock fail can be
LOS_FLAG_TO_TDO
• AMI violation
• LOS
• T4 DPLL locking status change
• Input clocks for T0 path validity change
• T0 selected input clock fail
• Input clocks for T4 path change to be no qualified input clock
• T0 DPLL operating mode switch
• External sync alarm
available
INT_POL
HZ_EN
INTERRUPT SUMMARY
Bit
MON_SW_PBO_CNFG
INTERRUPT_CNFG
Register
Address (Hex)
0C
0B
47
3.16
The main features supported by the T0 path are as follows:
The main features supported by the T4 path are as follows:
• Phase lock alarm;
• Forced or Automatic input clock selection/switch;
• 3 primary and 3 secondary, temporary DPLL operating modes,
• Automatic switch between starting, acquisition and locked band-
• Programmable DPLL bandwidths from 0.5 mHz to 560 Hz in 19
• Programmable damping factors: 1.2, 2.5, 5, 10 and 20;
• Fast loss, coarse phase loss, fine phase loss and hard limit
• Output phase and frequency offset limited;
• Automatic Instantaneous, Automatic Slow Averaged, Automatic
• PBO to minimize output phase transients;
• Programmable output phase offset;
• Low jitter multiple clock outputs with programmable polarity;
• Low jitter 2 kHz and 8 kHz frame sync signal outputs with pro-
• Master / Slave application to enable system protection against
• Forced or Automatic input clock selection/switch;
• Locking to T0 DPLL output;
• 3 DPLL operating modes, switched automatically or under exter-
• Programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and 560
• Programmable damping factor: 1.2, 2.5, 5, 10 and 20;
• Fast loss, coarse phase loss, fine phase loss and hard limit
• Output phase and frequency offset limited;
• Automatic Instantaneous holdover frequency offset;
• Low jitter multiple clock outputs with programmable polarity.
switched automatically or under external control;
widths/damping factors;
steps;
exceeding monitoring;
Fast Averaged or Manual holdover frequency offset acquiring;
grammable pulse width and polarity;
single device failure.
nal control;
Hz;
exceeding monitoring;
T0 AND T4 SUMMARY
SYNCHRONOUS ETHERNET WAN PLL
May 19, 2009
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