82V3380PFG IDT, Integrated Device Technology Inc, 82V3380PFG Datasheet - Page 96
82V3380PFG
Manufacturer Part Number
82V3380PFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3380PFG.pdf
(175 pages)
Specifications of 82V3380PFG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2
Programming Information
IDT82V3380
Address: 25H
Type: Read / Write
Default Value: X0000000
6 - 0
Bit
7
7
-
PRE_DIVN_VALUE[14:8]
PRE_DIVN_VAL
Name
UE14
-
6
PRE_DIVN_VAL
Reserved.
If the value in the PRE_DIVN_VALUE[14:0] bits is plus 1, the division factor for an input clock will be gotten. The input
clock is selected by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H).
A value from ‘0’ to ‘4BEF’ (Hex) can be written into, corresponding to a division factor from 1 to 19440. The others are
reserved. So the DivN Divider only supports an input clock whose frequency is lower than ( < ) 155.52 MHz.
The division factor setting should observe the following order:
1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits;
2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits.
UE13
5
PRE_DIVN_VAL
UE12
4
96
PRE_DIVN_VAL
UE11
3
Description
PRE_DIVN_VAL
UE10
2
SYNCHRONOUS ETHERNET WAN PLL
PRE_DIVN_VAL
UE9
1
PRE_DIVN_VAL
May 19, 2009
UE8
0
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