82V3380PFG IDT, Integrated Device Technology Inc, 82V3380PFG Datasheet - Page 60
82V3380PFG
Manufacturer Part Number
82V3380PFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3380PFG.pdf
(175 pages)
Specifications of 82V3380PFG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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dard except the following:
Table 43: JTAG Timing Characteristics
JTAG
IDT82V3380
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
The JTAG interface timing diagram is shown in
• The output boundary scan cells do not capture data from the
• The TRST pin is set low by default and JTAG is disabled in order
Symbol
core and the device does not support EXTEST instruction;
to be consistent with other manufacturers.
t
TCK
t
t
t
S
H
D
TCK
TMS
TDI
JTAG
TMS / TDI to TCK setup time
TCK to TMS / TDI Hold Time
TCK to TDO delay time
TCK period
Parameter
TDO
t
S
Figure 26. JTAG Interface Timing Diagram
Figure
26.
t
H
60
t
TCK
Min
100
25
25
t
D
Typ
SYNCHRONOUS ETHERNET WAN PLL
Max
50
May 19, 2009
Unit
ns
ns
ns
ns
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