AM79C972BVF AMD (ADVANCED MICRO DEVICES), AM79C972BVF Datasheet - Page 28

• Manufacturer Part Number: AM79C972BVF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVF

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The Am79C972 controller will not assert DEVSEL if it
detects an address match, but the PCI command is not
of the correct type. In memory mapped I/O mode, the
Am79C972 controller aliases all accesses to the I/O re-
sources of the command types Memory Read Multiple
and Memory Read Line to the basic Memory Read com-
mand. All accesses of the type Memory Write and In-
validate are aliased to the basic Memory Write
command. Eight-bit, 16-bit, and 32-bit non-burst trans-
actions are supported. The Am79C972 controller de-
codes all 32 address lines to determine which I/O
resource is accessed.
The typical number of wait states added to a slave I/O
or memory mapped I/O read or write access on the part
of the Am79C972 controller is six to seven clock cycles,
depending upon the relative phases of the internal Buff-
er Management Unit clock and the CLK signal, since
28
DEVSEL
FRAME
IDSEL
TRDY
STOP
C/BE
IRDY
CLK
PAR
AD
Figure 1. Slave Configuration Read
1
DEVSEL is sampled
ADDR
1010
2
PAR
3
4
BE
5
DATA
PAR
6
6
21485C-4
7
Am79C972
the internal Buffer Management Unit clock is a divide-
by-two version of the CLK signal.
The Am79C972 controller does not support burst trans-
fers for access to its I/O resources. When the host keeps
FRAME asserted for a second data phase, the
Am79C972 controller will disconnect the transfer.
The Am79C972 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardwired to 1. The Am79C972 controller
is capable of detecting an I/O or a memory-mapped
I/O cycle even when its address phase immediately fol-
lows the data phase of a transaction to a different target,
without any idle state in-between. There will be no con-
tention on the DEVSEL, TRDY, and STOP signals, since
the Am79C972 controller asserts DEVSEL on the sec-
ond clock after FRAME is asserted (medium timing) See
Figure 3 and Figure 4.
DEVSEL
FRAME
IDSEL
STOP
TRDY
C/BE
IRDY
PAR
CLK
AD
Figure 2. Slave Configuration Write
1
ADDR
1011
2
PAR
3
4
DATA
BE
5
PAR
6
21485C-5
7