AM79C972BVF AMD (ADVANCED MICRO DEVICES), AM79C972BVF Datasheet - Page 83

• Manufacturer Part Number: AM79C972BVF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BVF

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The LED pins can be configured to operate in either
open-drain mode (active low) or in totem-pole mode
Address
Word
00h*
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
3Fh
01h
02h
03h
04h
05h
06h
07h
08h
09h
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
20h
21h
Address
Byte
0Bh
0Dh
0Fh
1Bh
1Dh
1Fh
2Bh
2Dh
2Fh
3Bh
3Dh
3Fh
7Fh
01h
03h
05h
07h
09h
11h
13h
15h
17h
19h
21h
23h
25h
27h
29h
31h
33h
35h
75h
39h
41h
43h
2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3)
station physical address for this node.
4th byte of the node address
6th byte of the node address
CSR116[15:8] (OnNow Misc. Config.)
Hardware ID; must be 11h if compatibility to
AMD drivers is desired
User programmable space
MSB of two-byte checksum, which is the sum
of bytes 00h-0Bh and bytes 0Eh and 0Fh
Must be ASCII “W” (57h) if compatibility to
AMD driver software is desired
BCR2[15:8] (Miscellaneous Configuration)
BCR4[15:8] (Link Status LED)
BCR5[15:8] (LED1 Status)
BCR6[15:8] (LED2 Status)
BCR7[15:8] (LED3 Status)
BCR9[15:8] (Full-Duplex Control)
BCR18[15:8] (Burst and Bus Control)
BCR22[15:8] (PCI Latency)
BCR23[15:8] (PCI Subsystem Vendor ID)
BCR24[15:8] (PCI Subsystem ID)
BCR25[15:8] (SRAM Size)
BCR26[15:8] (SRAM Boundary)
BCR27[15:8] (SRAM Interface Control)
BCR32[15:8] (MII Control and Status)
BCR33[15:8] (MII Address)
BCR35[15:8] (PCI Vendor ID)
BCR36[15:8] (Conf. Space byte 43h alias)
BCR37[15:8] (DATA_SCALE alias 0)
BCR38[15:8] (DATA_SCALE alias 1)
BCR39[15:8] (DATA_SCALE alias 2)
BCR40[15:8] (DATA_SCALE alias 3)
BCR41[15:8] (DATA_SCALE alias 4)
BCR42[15:8] (DATA_SCALE alias 0)
BCR43[15:8] (DATA_SCALE alias 0)
BCR44[15:8] (DATA_SCALE alias 0)
Checksum adjust byte for the 68 bytes of the
EEPROM contents. Checksum of the 68 bytes
of the EEPROM should total FFh.
Reserved
Most Significant Byte
Unused locations - Ignored by device
Table 10.
Am79C972
EEPROM Map
(active high). The output can be stretched to allow the
human eye to recognize even short events that last only
several microseconds. After H_RESET, the four LED
outputs are configured as shown in Table 11.
Address
Byte
0Ch
1Ch
2Ch
3Ch
00h
02h
04h
06h
08h
0Ah
0Eh
10h
12h
14h
16h
18h
1Ah
1Eh
20h
22h
24h
26h
28h
2Ah
2Eh
30h
32h
34h
36h
38h
3Ah
3Eh
40h
42h
7Eh
First byte of the ISO 8802-3 (IEEE/ANSI
802.3) station physical address for this
node, where “first byte” refers to the first
byte to appear on the 802.3 medium.
3rd byte of the node address
5th byte of the node address
CSR116[7:0] (OnNow Misc. Config.)
Reserved location: must be 00h
User programmable space
LSB of two-byte checksum, which is the
sum of bytes 00h-0Bh and bytes 0Eh and
0Fh
Must be ASCII “W” (57h) if compatibility to
AMD driver software is desired
BCR2[7:0] (Miscellaneous Configuration)
BCR4[7:0] (Link Status LED)
BCR5[7:0] (LED1 Status)
BCR6[7:0] (LED2 Status)
BCR7[7:0] (LED3 Status)
BCR9[7:0] (Full-Duplex Control)
BCR18[7:0] (Burst and Bus Control)
BCR22[7:0] (PCI Latency)
BCR23[7:0] (PCI Subsystem Vendor ID)
BCR24[7:0] (PCI Subsystem ID)
BCR25[7:0] (SRAM Size)
BCR26[7:0] (SRAM Boundary)
BCR27[7:0] (SRAM Interface Control)
BCR32[7:0] (MII Control and Status)
BCR33[7:0] (MII Address)
BCR35[7:0] (PCI Vendor ID)
BCR36[7:0] (Conf. Space byte 42h alias)
BCR37[7:0] (Conf. Space byte 47h 0 alias)
BCR38[7:0] (Conf. Space. byte 47h 1 alias)
BCR39[7:0] (Conf. Space. byte 47h 2 alias)
BCR40[7:0] (Conf. Space. byte 47h 3 alias)
BCR41[7:0] (Conf. Space. byte 47h 4 alias)
BCR42[7:0] (Conf. Space. byte 47h 5 alias)
BCR43[7:0] (Conf. Space. byte 47h 6 alias)
BCR44[7:0] (Conf. Space. byte 47h 7 alias)
Reserved location: must be 00h
Reserved
Least Significant Byte
83