MT41J128M8JP-125:G Micron Technology Inc, MT41J128M8JP-125:G Datasheet - Page 99

• Manufacturer Part Number: MT41J128M8JP-125:G
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J128M8JP-125:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 46: DLL Disable
Table 66:
Input Clock Frequency Change
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
DQ BL8 DLL disable
DQ BL8 DLL disable
DQS, DQS# DLL off
DQS, DQS# DLL off
DQS, DQS# DLL on
DQ BL8 DLL on
Command
Address
CK#
CK
READ Electrical Characteristics, DLL Disable Mode
READ
Valid
T0
NOP
T1
When the DDR3 SDRAM is initialized, it requires the clock to be stable during most
normal states of operation. This means that after the clock frequency has been set to the
stable state, the clock period is not allowed to deviate except what is allowed for by the
clock jitter and spread spectrum clocking (SSC) specifications.
The input clock frequency can be changed from one stable clock rate to another under
two conditions: self refresh mode and precharge power-down mode. Outside of these
two modes, it is illegal to change the clock frequency. For the self refresh mode condi-
tion, when the DDR3 SDRAM has been successfully placed into self refresh mode and
t
becomes a “Don’t Care,” changing the clock frequency is permissible, provided the new
clock frequency is stable prior to
for the sole purpose of changing the clock frequency, the self refresh entry and exit spec-
ifications must still be met.
The precharge power-down mode condition is when the DDR3 SDRAM is in precharge
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a
logic LOW or R
R
and CKE must be at a logic LOW. A minimum of
before the clock frequency can change. The DDR3 SDRAM input clock frequency is
allowed to change only within the minimum and maximum operating frequency
specified for the particular speed grade (
input clock frequency change, CKE must be held at a stable LOW level. When the input
clock frequency is changed, a stable clock must be provided to the DRAM
precharge power-down may be exited. After precharge power-down is exited and
Parameter
CKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the clock
t
Access window of DQS from CK, CK#
TT
DQSCK Timing
_
RL (DLL disable) = AL + (CL - 1) = 5
NOM
NOP
T2
RL = AL + CL = 6 (CL = 6, AL = 0)
and R
TT
CL = 6
TT
NOP
T3
_
_
NOM
WR
are in an off state prior to entering precharge power-down mode,
and R
NOP
T4
TT
99
_
WR
t
CKSRX. When entering and exiting self refresh mode
NOP
T5
must be disabled via MR1 and MR2. This ensures
t DQSCK (
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DI
b
t
t
DQSCK (
CK [AVG] MIN to
DLL
t DQSCK (
Symbol
b + 1
NOP
_
DI
T6
DI
b
DIS
) MIN
DI
b
DLL
t
1Gb: x4, x8, x16 DDR3 SDRAM
CKSRE must occur after CKE goes LOW
b + 2
_
b + 1
DLL
DI
DIS
DI
) MAX
b + 1
_
DI
DIS
NOP
b + 3
b + 2
T7
DI
DI
)
b + 2
DI
b + 4
b + 3
DI
DI
t
CK [AVG] MAX). During the
b + 3
DI
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b + 4
NOP
Min
b + 5
DI
T8
DI
1
b + 4
DI
b + 6
b + 5
DI
DI
Transitioning Data
b + 5
DI
Max
NOP
b + 7
b + 6
T9
DI
DI
10
t
Commands
CKSRX before
b + 6
DI
b + 7
DI
b + 7
DI
t
Units
Don’t Care
XP has
T10
NOP
ns