PPC405GP-3DE133C Applied Micro Circuits Corporation, PPC405GP-3DE133C Datasheet - Page 30

• Manufacturer Part Number: PPC405GP-3DE133C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GP-3DE133C

• Family Name: 405GP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / RoHS Status: Not Compliant

405GP – Power PC 405GP Embedded Processor
Signal Functional Description
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
30
PCI Interface
PCIC3:0[BE3:0]
PCIINT[PerWE]
PCIReq0[Gnt]
Signal Name
PCIAD31:0
PCIDevSel
PCIReq1:5
PCIFrame
PCITRDY
PCIParity
PCIReset
PCIIRDY
PCIIDSel
PCIStop
PCISErr
PCIPErr
PCIClk
PCI Address/Data Bus. Multiplexed address and data bus.
PCI bus command and byte enables.
PCI parity. Parity is even across PCIAD0:31 and PCIC0:3[BE0:3].
PCIParity is valid one cycle after either an address or data phase.
The PCI device that drove PCIAD0:31 is responsible for driving
PCIParity on the next PCI bus clock.
PCIFrame is driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
PCIIRDY is driven by the current PCI bus master. Assertion of
PCIIRDY indicates that the PCI initiator is ready to transfer data.
The target of the current PCI transaction drives PCITRDY. Assertion
of PCITRDY indicates that the PCI target is ready to transfer data.
The target of the current PCI transaction can assert PCIStop to
indicate to the requesting PCI master that it wants to end the current
transaction.
PCIDevSel is driven by the target of the current PCI transaction. A
PCI target asserts PCIDevSel when it has decoded an address and
command encoding and claims the transaction.
PCIIDSel is used during configuration cycles to select the PCI slave
interface for configuration.
PCISErr is used for reporting address parity errors or catastrophic
failures detected by a PCI target.
PCIPErr is used for reporting data parity errors on PCI transactions.
PCIPErr is driven active by the device receiving PCIAD0:31,
PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the data in
which bad parity is detected.
PCIClk is used as the asynchronous PCI clock when in
asynchronous mode. It is unused when the PCI interface is operated
synchronously with the PLB bus.
PCI specific reset.
PCI interrupt. Open-drain output (two states; 0 or open circuit)
or
Peripheral write enable. Low when any of the four PerWBE0:3 write
byte enables are low.
Multipurpose signal, used as PCIReq0 when internal arbiter is used,
and as Gnt when external arbiter is used.
Used as PCIReq1:5 input when internal arbiter is used.
(Part 1 of 8)
Description
Revision 2.05 – August 19, 2008
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Data Sheet
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Type
Notes
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AMCC