PPC405GP-3DE133C Applied Micro Circuits Corporation, PPC405GP-3DE133C Datasheet - Page 51

• Manufacturer Part Number: PPC405GP-3DE133C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GP-3DE133C

• Family Name: 405GP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / RoHS Status: Not Compliant

Revision 2.05 – August 19, 2008
AMCC
PPC405GP Strapping Pin Assignments
PCI Divider from PLB
External Bus Divider from PLB
ROM Width
ROM Location
PCI Asynchronous Mode Enable
PCI Arbiter Enable
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using
PPC405GP. These bits are shown for information only; and do not require modification except in special clocking circumstances such as
spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GP, visit the technical
documents area of the AMCC PowerPC web site.
Specifications” on page 42. Further requirements are detailed in the Clocking chapter of the PowerPC 405GP Embedded Processor
User’s Manual.
three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
Data Sheet
3
Function
2, 3
2
PPC405GP Peripheral Attach
Internal Arbiter Disabled
Synchronous PCI Mode
Internal Arbiter Enabled
PPC405GP PCI Attach
Asynchronous Mode
(Part 2 of 2)
16-bit ROM
32-bit ROM
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 2
Divide by 3
Divide by 4
Divide by 5
405GP – Power PC 405GP Embedded Processor
8-bit ROM
Reserved
Option
GPIO4[TS2O]
GPIO1[TS1E]
UART1_Tx
EMCTxErr
HoldAck
ExtAck
AF18
AC2
D18
K25
U2
Y3
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
Ball Strapping
GPIO2[TS2E]
UART1_RTS/
UART1_DTR
EMCTxEn
AD2
C20
K23
0
1
0
1
0
1
0
1
0
1
0
1
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