IDT82V3280DQ IDT, Integrated Device Technology Inc, IDT82V3280DQ Datasheet - Page 29

• Manufacturer Part Number: IDT82V3280DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3280DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP EP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8
selection, it can be switched by setting the related registers (refer to
Chapter 3.6.1 External Fast Selection (T0 only)
Selection) any time. In this case, whether the input clock is qualified for
DPLL locking does not affect the clock switch. If the T4 selected input
clock is a T0 DPLL output, it can only be switched by setting the
T0_FOR_T4 bit.
clock switch depends on its validity, priority and locking allowance con-
figuration. If the current selected input clock is disqualified, a new quali-
fied input clock may be switched to.
3.8.1
clock quality monitoring (refer to
toring). When all of the following conditions are satisfied, the input clock
is valid; otherwise, it is invalid.
from that of the T4 selected input clock. The validity qualification of the
T4 selected input clock is the same as the above. The T0 selected input
clock is valid when all of the above and the following conditions are sat-
isfied; otherwise, it is invalid.
≥ n ≥ 1). When the input clock validity changes (from ‘valid’ to ‘invalid’ or
from ‘invalid’ to ‘valid’), the INn
interrupt will be generated.
selected input clock changes from ‘valid’ to ‘invalid’, the
T0_MAIN_REF_FAILED
bit is ‘1’, an interrupt will be generated. This interrupt can also be indi-
cated by hardware - the TDO pin, as determined by the
LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this
interrupt, it will be set high when this interrupt is generated and will
remain high until this interrupt is cleared.
3.8.2
input clock switch is different from T4 input clock switch.
Functional Description
IDT82V3280
If the input clock is selected by External Fast selection or by Forced
When the input clock is selected by Automatic selection, the input
For all the input clocks, the validity depends on the results of input
The validity qualification of the T0 selected input clock is different
The validities of all the input clocks are indicated by the INn
When the T0 selected input clock has failed, i.e., the validity of the T0
When the device is configured as Automatic input clock selection, T0
• No LOS (the AMI1_LOS / AMI2_LOS bit is ‘0’);
• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is
• If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
• No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’;
• If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
‘0’);
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
misses less than (<) 2 consecutive clock cycles; if the
ULTR_FAST_SW bit is ‘0’, this condition is ignored.
SELECTED INPUT CLOCK SWITCH
INPUT CLOCK VALIDITY
SELECTED INPUT CLOCK SWITCH
1
bit will be set. If the T0_MAIN_REF_FAILED
2
Chapter 3.5 Input Clock Quality Moni-
bit will be set. If the INn
&
Chapter 3.6.2 Forced
3
bit is ‘1’, an
1
bit (14
2
29
as selected by the REVERTIVE_MODE bit.
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
different from that for T4 selection, as shown in
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4
Selection
satisfied.
3.8.2.1
another qualified input clock with a higher priority than the current
selected input clock is available.
fied:
switch. If more than one qualified input clock INn is available and has the
same priority, the input clock with the smallest ‘n’ is selected.
T0
T4
The input clock is disqualified if any of the above conditions is not
In summary, the selected input clock can be switched by:
In Revertive switch, the selected input clock is switched when
The selected input clock is switched if any of the following is satis-
A qualified input clock with the highest priority is selected by revertive
For T0 path, Revertive and Non-Revertive switches are supported,
For T4 path, only Revertive switch is supported.
The difference between Revertive and Non-Revertive switches is
Conditions of the qualified input clocks available for T0 selection are
• Valid, i.e., the INn
• Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits
• Locking to the input clock is allowed, i.e., the corresponding INn_VALID
• Valid (all the validity conditions listed in
• Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits
• Locking to the input clock is allowed, i.e., the corresponding INn_VALID
• External Fast selection (supported by T0 path only);
• Forced selection;
• Revertive switch;
• Non-Revertive switch (supported by T0 path only);
• T4 DPLL locked to T0 DPLL output (supported by T4 path only).
• the selected input clock is disqualified;
• another qualified input clock with a higher priority than the
Conditions of Qualified Input Clocks Available for T0 & T4 Selection
are not ‘0000’;
bit is ‘0’.
ity
are not ‘0000’;
bit is ‘0’.
selected input clock is available.
are satisfied);
Revertive Switch
1
bit is ‘1’;
Chapter 3.8.1 Input Clock Valid-
Table
13:
March 02, 2009
WAN PLL