IDT82V3280DQ IDT, Integrated Device Technology Inc, IDT82V3280DQ Datasheet - Page 77
IDT82V3280DQ
Manufacturer Part Number
IDT82V3280DQ
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V3280DQ.pdf
(167 pages)
Specifications of IDT82V3280DQ
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP EP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Part Number:
IDT82V3280DQ
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SIL
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INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
Programming Information
IDT82V3280
Address: 11H
Type: Read / Write
Default Value: 00000000
Address: 10H
Type: Read / Write
Default Value: 00000000
T0_OPERATING
5 - 0
7 - 0
Bit
Bit
7
6
_MODE
IN8
7
7
T0_OPERATING_MODE
T0_MAIN_REF_FAILED
Name
INn
T0_MAIN_REF_F
Name
INn
IN7
6
AILED
6
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b7~0, 0DH) is ‘1’. Here n is any one of 8 to 1.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b5~0, 0EH) is ‘1’. Here n
is any one of 14 to 9.
0: Disabled. (default)
1: Enabled.
IN6
5
IN14
5
IN5
4
IN13
4
77
IN4
IN12
3
3
Description
Description
IN3
IN11
2
2
IN10
IN2
1
1
March 02, 2009
IN9
IN1
0
0
WAN PLL
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