XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet
XC6VSX475T-2FFG1759E
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DS152 (v3.2) April 1, 2011 Virtex-6 FPGA Electrical Characteristics Virtex®-6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA DC and AC characteristics are specified in commercial, extended, and industrial ...
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Table 2: Recommended Operating Conditions Symbol Internal supply voltage relative to GND for all devices except -1L devices. For -1L commercial temperature range devices: internal supply voltage relative V to GND 0°C to +85°C CCINT j For -1L ...
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... CCOQ CCO supply current XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T DS152 (v3.2) April 1, 2011 Product Specification Virtex-6 FPGA Data Sheet: DC and Switching Characteristics = 85°C because the majority of designs operate near the high end of j Table 4 ...
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... XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes: 1. Typical values are specified at nominal voltage, 85°C junction temperatures (T typical values as commercial (C) grade devices at 85°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values. -1L industrial grade devices have the values specified in this column ...
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... Table 5: Power-On Current for Virtex-6 Devices Device XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. Use the XPOWER™ Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents. ...
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SelectIO™ DC Input and Output Levels Values for V and V are recommended input voltages. Values for operating conditions at the V and V OL all standards meet their specifications. The selected standards are tested at a ...
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HT DC Specifications (HT_25) Table Specifications Symbol DC Parameter V Supply Voltage CCO V Differential Output Voltage OD V Change in V Magnitude Output Common Mode Voltage OCM V Change in V ...
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LVPECL DC Specifications (LVPECL_25) These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The V levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant ...
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GTX Transceiver Specifications GTX Transceiver DC Characteristics Table 13: Absolute Maximum Ratings for GTX Transceivers Symbol Analog supply voltage for the GTX transmitter and receiver circuits relative to MGTAVCC GND Analog supply voltage for the GTX transmitter and receiver termination ...
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Table 16: GTX Transceiver Quiescent Supply Current (per Lane) Symbol I Quiescent MGTAVTT supply current for one GTX transceiver MGTAVTTQ I Quiescent MGTAVCC supply current for one GTX transceiver MGTAVCCQ Notes: 1. Device powered and unconfigured. 2. Currents for conditions ...
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X-Ref Target - Figure P–N –V Table 18 summarizes the DC specifications of the clock input of the GTX transceiver. Consult UG366:Virtex-6 FPGA GTX Transceivers User Guide for further details. Table 18: GTX Transceiver Clock DC Input ...
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Table 21: GTX Transceiver Reference Clock Switching Characteristics Symbol Description F Reference clock frequency range GCLK T Reference clock rise time RCLK T Reference clock fall time FCLK T Reference clock duty cycle DCREF Clock recovery frequency acquisition T LOCK ...
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Table 23: GTX Transceiver Transmitter Switching Characteristics Symbol F Serial data rate range GTXTX T TX Rise time RTX T TX Fall time FTX T TX lane-to-lane skew LLSKEW V Electrical idle amplitude TXOOBVDPP T Electrical idle transition time TXOOBTRANSITION ...
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Table 24: GTX Transceiver Receiver Switching Characteristics Symbol F Serial data rate GTXRX T Time for RXELECIDLE to respond to loss or restoration of data RXELECIDLE RX OOB detect threshold peak-to-peak OOBVDPP Receiver spread-spectrum RX SST (1) tracking RX Run ...
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GTH Transceiver Specifications GTH Transceiver DC Characteristics Table 25: Absolute Maximum Ratings for GTH Transceivers Symbol Analog supply voltage for the GTH transmitter, receiver, and common analog MGTHAVCC circuits MGTHAVCCRX Analog supply voltage for the GTH receiver circuits and common ...
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Figure 4 shows the timing parameters in X-Ref Target - Figure 4 MGTHAVCC (1.1V DC) MGTHAVCCRX (1.1V DC) MGTHAVCCPLL (1.8V DC) MGTHAVTT (1.2V DC) Figure 4: GTH Transceiver Power Supply Power-On Sequencing Table 28: GTH Transceiver Supply Current Symbol I ...
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GTH Transceiver DC Input and Output Levels Table 30 summarizes the DC output specifications of the GTH transceivers in Virtex-6 FPGAs. Consult UG371:Virtex-6 FPGA GTH Transceivers User Guide for further details. Table 30: GTH Transceiver DC Specifications Symbol DC Parameter ...
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GTH Transceiver Switching Characteristics Consult UG371:Virtex-6 FPGA GTH Transceivers User Guide for further information. Table 32: GTH Transceiver Maximum Data Rate and PLL Frequency Range Symbol Description F Maximum GTH transceiver data rate GTHMAX F Minimum GTH transceiver data rate ...
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Table 35: GTH Transceiver User Clock Switching Characteristics Symbol Description F TXUSERCLKOUT maximum frequency TXOUT F RXUSERCLKOUT maximum frequency RXOUT F TXUSERCLKIN maximum frequency TXIN F RXUSERCLKIN maximum frequency RXIN Notes: 1. Clocking must be implemented as described in UG371:Virtex-6 ...
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Table 37: GTH Transceiver Receiver Switching Characteristics Symbol R Run length (CID) XRL R Data/REFCLK PPM offset tolerance XPPMTOL (1)(2)(3)(4) SJ Jitter Tolerance JT_SJ Sinusoidal Jitter 11.18 JT_SJ Sinusoidal Jitter 10.32 JT_SJ Sinusoidal Jitter 9.95 JT_SJ Sinusoidal Jitter 2.667 JT_SJ ...
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Integrated Interface Block for PCI Express Designs Switching Characteristics More information and documentation on solutions for PCI Express designs can be found at: http://www.xilinx.com/technology/protocols/pciexpress.htm Table 39: Maximum Performance for PCI Express Designs Symbol F Pipe clock maximum frequency PIPECLK F ...
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Table 40: Analog-to-Digital Specifications (Cont’d) Parameter Symbol (3) Analog Inputs Dedicated Analog Inputs Input Voltage Range Auxiliary Analog Inputs Input Voltage Range AUXP[0] AUXN[0] AUXP[15] /V AUXN[15 –40°C to ...
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Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as ...
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... Table 42: Virtex-6 Device Speed Grade Designations Speed Grade Designations Device Advance XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T www.xilinx.com Preliminary Production -3, -2, -1, -1L -3, -2, -1, -1L -3, -2, -1, -1L -3, -2, -1, -1L -3, -2, -1, -1L ...
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... ISE 12.1 v1.06 XC6VLX240T ISE 12.1 v1.06 XC6VLX365T XC6VLX550T N/A XC6VLX760 N/A XC6VSX315T ISE 12.2 v1.08 XC6VSX475T N/A XC6VHX250T XC6VHX255T ISE 13.1 v1.14 using the ISE 13.1 software update XC6VHX380T XC6VHX565T N/A Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status. ...
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IOB Pad Input/Output/3-State Switching Characteristics Table 44 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays described as the delay from IOB pad through the input buffer ...
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Table 44: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS25, Fast LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Fast ...
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Table 44: IOB Switching Characteristics (Cont’d) I/O Standard LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 LVPECL_25 HSTL_I_12 HSTL_I_DCI HSTL_II_DCI HSTL_II_T_DCI HSTL_III_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_II _T_DCI_18 HSTL_III_DCI_18 DIFF_HSTL_I_18 DIFF_HSTL_I_DCI_18 DIFF_HSTL_I DIFF_HSTL_I_DCI DIFF_HSTL_II_18 DIFF_HSTL_II_DCI_18 DIFF_HSTL_II _T_DCI_18 DIFF_HSTL_II DIFF_HSTL_II_DCI SSTL2_I_DCI SSTL2_II_DCI SSTL2_II_T_DCI SSTL18_I SSTL18_II SSTL18_I_DCI SSTL18_II_DCI SSTL18_II_T_DCI ...
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Table 44: IOB Switching Characteristics (Cont’d) I/O Standard DIFF_SSTL18_I DIFF_SSTL18_I_DCI DIFF_SSTL18_II DIFF_SSTL18_II_DCI DIFF_SSTL18_II_T_DCI DIFF_SSTL15 DIFF_SSTL15_DCI DIFF_SSTL15_T_DCI Table 45: IOB 3-state ON Output Switching Characteristics (T Symbol T T input to Pad high-impedance IOTPHZ DS152 (v3.2) April 1, 2011 Product Specification ...
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I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 46 shows the test setup parameters used for measuring input delay. Table 46: Input Delay Measurement Methodology Description LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V HSTL (High-Speed Transceiver Logic), Class I & ...
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Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately ...
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Table 47: Output Delay Measurement Methodology (Cont’d) Description HT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVDCI/HSLVDCI, 2.5V LVDCI/HSLVDCI, 1.8V LVDCI/HSLVDCI, 1.5V HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI HSTL, Class III, with DCI ...
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Table 49: OLOGIC Switching Characteristics Symbol Setup/Hold T /T D1/D2 pins Setup/Hold with respect to CLK ODCK OCKD T /T OCE pin Setup/Hold with respect to CLK OOCECK OCKOCE pin Setup/Hold with respect to CLK OSRCK OCKSR ...
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Input Serializer/Deserializer Switching Characteristics Table 50: ISERDES Switching Characteristics Symbol Setup/Hold for Control Lines BITSLIP pin Setup/Hold with respect to CLKDIV ISCCK_BITSLIP ISCKC_BITSLIP ( pin Setup/Hold with respect to CLK (for CE1) ISCCK_CE ...
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Output Serializer/Deserializer Switching Characteristics Table 51: OSERDES Switching Characteristics Symbol Setup/Hold input Setup/Hold with respect to CLKDIV OSDCK_D OSCKD_D ( input Setup/Hold with respect to CLK OSDCK_T OSCKD_T ( input Setup/Hold ...
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Input/Output Delay Switching Characteristics Table 52: Input/Output Delay Switching Characteristics Symbol IDELAYCTRL T Reset to Ready for IDELAYCTRL DLYCCO_RDY F REFCLK frequency = 200.0 IDELAYCTRL_REF REFCLK frequency = 300.0 IDELAYCTRL_REF_PRECISION REFCLK precision T Minimum Reset pulse width IDELAYCTRL_RPW IODELAY T ...
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CLB Switching Characteristics Table 53: CLB Switching Characteristics Symbol Combinatorial Delays T An – Dn LUT address to A ILO An – Dn LUT address to AMUX/CMUX An – Dn LUT address to BMUX_A T An – Dn inputs to ...
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Table 53: CLB Switching Characteristics (Cont’d) Symbol Set/Reset T SR input minimum pulse width SRMIN T Delay from SR input to AQ – DQ flip-flops RQ T Delay from CE input to AQ – DQ flip-flops CEO F Toggle frequency ...
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CLB Shift Register Switching Characteristics (SLICEM Only) Table 55: CLB Shift Register Switching Characteristics Symbol Sequential Delays T Clock to A – D outputs REG T Clock to AMUX – DMUX output REG_MUX T Clock to DMUX output via M31 ...
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Block RAM and FIFO Switching Characteristics Table 56: Block RAM and FIFO Switching Characteristics Symbol Block RAM and FIFO Clock-to-Out Delays (1) T and T Clock CLK to DOUT output (without output RCKO_DO RCKO_DO_REG register) Clock CLK to DOUT output ...
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Table 56: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol T /T Write Enable (WE) input (Block RAM only) RCCK_WE RCKC_WE T /T WREN FIFO inputs RCCK_WREN RCKC_WREN T /T RDEN FIFO inputs RCCK_RDEN RCKC_RDEN Reset Delays T Reset RST ...
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Table 57: DSP48E1 Switching Characteristics (Cont’d) Symbol Setup and Hold Times of Data Pins to the Pipeline Register Clock T / DSPDCK_{A, ACIN, B, BCIN}_MREG_MULT T DSPCKD_{A, ACIN, B, BCIN}_MREG_MULT DSPDCK_{A, D}_ADREG DSPCKD_{A, D}_ADREG Setup and Hold ...
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Table 57: DSP48E1 Switching Characteristics (Cont’d) Symbol Combinatorial Delays from Input Pins to Cascading Output Pins T DSPDO_{A; B}_{ACOUT; BCOUT} T DSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MULT T DSPDO_D_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MULT T DSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT} T DSPDO__{C, CARRYIN}_{PCOUT, CARRYCASCOUT,MULTSIGNOUT} Combinatorial Delays ...
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Table 57: DSP48E1 Switching Characteristics (Cont’d) Symbol Clock to Outs from Input Register Clock to Output Pins T DSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT T DSPCKO_{P, CARRYOUT}_{AREG, BREG} T DSPCKO_{P, CARRYOUT}_CREG T DSPCKO_{P, CARRYOUT}_DREG_MULT Clock to Outs from Input Register Clock to Cascading ...
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Table 58: Configuration Switching Characteristics (Cont’d) Symbol Master/Slave Serial Mode Programming Switching T /T DIN Setup/Hold, slave mode DCCK CCKD T /T DIN Setup/Hold, master mode DSCCK SCCKD T DOUT at 2.5V CCO DOUT at 1.8V F Maximum CCLK frequency, ...
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Table 58: Configuration Switching Characteristics (Cont’d) Symbol BPI Master Flash Mode Programming Switching (2) T ADDR[25:0], RS[1:0], FCS_B, FOE_B, BPICCO FWE_B outputs valid after CCLK rising edge at 2.5V ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge ...
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Clock Buffers and Networks Table 59: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol ( pins Setup/Hold BCCCK_CE BCCKC_CE ( pins Setup/Hold BCCCK_S BCCKC_S (2) T BUFGCTRL delay from I0/ BCCKO_O Maximum Frequency ...
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MMCM Switching Characteristics Table 63: MMCM Specification Symbol F Maximum Input Clock Frequency INMAX F Minimum Input Clock Frequency INMIN F Maximum Input Clock Period Jitter INJITTER (2) F Allowable Input Duty Cycle: 10—49 MHz INDUTY Allowable Input Duty Cycle: ...
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... DS152 (v3.2) April 1, 2011 Product Specification Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Description is 315 MHz. is 0.036 MHz. OUTMIN Device XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T www.xilinx.com Speed Grade - -1L 0.32 0.34 0.38 0.38 Speed Grade ...
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... XC6VLX130T 2.24 2.39 XC6VLX195T 2.24 2.40 XC6VLX240T 2.24 2.40 XC6VLX365T 2.25 2.42 XC6VLX550T N/A 2.43 XC6VLX760 N/A 2.42 XC6VSX315T 2.23 2.38 XC6VSX475T N/A 2.30 XC6VHX250T 2.25 2.41 XC6VHX255T 2.35 2.51 XC6VHX380T 2.27 2.43 XC6VHX565T N/A 2.41 www.xilinx.com Units -1 -1L 2.77 2. ...
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... XC6VLX130T 1.31/ –0.08 XC6VLX195T 1.36/ –0.11 XC6VLX240T 1.36/ –0.11 XC6VLX365T 1.79/ –0.28 XC6VLX550T N/A XC6VLX760 N/A XC6VSX315T 1.75/ –0.09 XC6VSX475T N/A XC6VHX250T 1.93/ –0.22 XC6VHX255T 1.81/ –0.33 XC6VHX380T 1.93/ –0.11 XC6VHX565T N/A www.xilinx.com Speed Grade Units -2 -1 -1L (1) 1.44/ 1.75/ 2 ...
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... XC6VLX365T 1.55/ 1.67/ –0.18 –0.18 XC6VLX550T N/A 1.84/ –0.17 XC6VLX760 N/A 2.26/ –0.13 XC6VSX315T 1.56/ 1.68/ –0.18 –0.18 XC6VSX475T N/A 1.85/ –0.23 XC6VHX250T 1.52/ 1.64/ –0.17 –0.17 XC6VHX255T 1.52/ 1.64/ –0.12 –0.12 XC6VHX380T 1.68/ 1.81/ –0.16 –0.16 XC6VHX565T N/A 1.81/ – ...
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... XC6VLX365T 1.66/ 1.79/ –0.25 –0.25 XC6VLX550T N/A 1.97/ –0.24 XC6VLX760 N/A 2.39/ –0.20 XC6VSX315T 1.67/ 1.80/ –0.25 –0.25 XC6VSX475T N/A 1.98/ –0.29 XC6VHX250T 1.63/ 1.76/ –0.24 –0.24 XC6VHX255T 1.63/ 1.76/ –0.19 –0.19 XC6VHX380T 1.80/ 1.94/ –0.23 –0.23 XC6VHX565T N/A 1.94/ – ...
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... Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Device All 0.12 (2) XC6VLX75T 0.15 XC6VLX130T 0.25 XC6VLX195T 0.26 XC6VLX240T 0.26 XC6VLX365T 0.28 XC6VLX550T N/A XC6VLX760 N/A XC6VSX315T 0.27 XC6VSX475T N/A XC6VHX250T 0.25 XC6VHX255T 0.35 XC6VHX380T 0.45 XC6VHX565T N/A All 0.08 All 0.03 All 0.10 All 0.15 www.xilinx.com Speed Grade -3 ...
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... Package trace length information is available for these device/package combinations. This information can be used to deskew the package. DS152 (v3.2) April 1, 2011 Product Specification Virtex-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T XC6VHX250T XC6VHX255T XC6VHX380T XC6VHX565T www.xilinx.com Package Value Units FF484 95 ps FF784 146 ps ...
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Table 72: Sample Window Symbol T Sampling Error at Receiver Pins SAMP T Sampling Error at Receiver Pins using SAMP_BUFIO (2) BUFIO Notes: 1. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, ...
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... The specification change in version 2.9, Transceiver User Guide, Family Data Sheet (SYSMON DCLK), and JTAG ID Changes In this version (2.10), -1L(I) data is added to Table 43 XC6VSX475T devices using ISE 12.3 software with current speed specifications. Revised the XC6VLX760 -1L speed specification for T 01/17/11 2.11 Changed in software with current speed specifications ...
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... Removed note 1 from Added maximum specifications to typical values and notes in added values for T Table 37 03/21/11 3.1 Updated the XC6VLX550T, XC6VLX760, XC6VSX475T, and XC6VHX380T devices, and added XC6VHX565T. Updated Table 04/01/11 3.2 Added Tj values for C, E, and I temperature ranges to Updated F Designated the data sheet as ...