XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 37

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XC6VSX475T-2FFG1759E

Manufacturer Part Number
XC6VSX475T-2FFG1759E
Description
IC FPGA VIRTEX 1759FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

Number Of Logic Elements/cells
476160
Number Of Labs/clbs
37200
Total Ram Bits
39223296
Number Of I /o
840
Number Of Gates
-
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1759-BBGA, FCBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
XC6VSX475T-2FFG1759I
XC6VSX475T-2FFG1759I

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC6VSX475T-2FFG1759E
Manufacturer:
XilinxInc
Quantity:
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Part Number:
XC6VSX475T-2FFG1759E
Manufacturer:
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Quantity:
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Part Number:
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0
CLB Switching Characteristics
Table 53: CLB Switching Characteristics
DS152 (v3.2) April 1, 2011
Product Specification
Combinatorial Delays
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Sequential Delays
T
T
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
T
T
T
T
AXA
AXB
AXC
AXD
AXCY
ILO
ITO
BXB
BXD
CXC
CXD
DXD
OPCYA
OPCYB
OPCYC
OPCYD
BXCY
CXCY
DXCY
BYP
CINA
CINB
CINC
CIND
CKO
SHCKO
DICK
CECK_CLB
CKCE_CLB
SRCK
CINCK
/T
/T
Symbol
/T
CKDI
CKSR
CKCIN
/
An – Dn LUT address to A
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
Clock to AQ – DQ outputs
Clock to AMUX – DMUX outputs
A – D input to CLK on A – D Flip Flops
CE input to CLK on A – D Flip Flops
SR input to CLK on A – D Flip Flops
CIN input to CLK on A – D Flip Flops
Description
www.xilinx.com
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
–0.07
0.30/
0.20/
0.39/
0.16/
0.06
0.18
0.28
0.59
0.31
0.35
0.39
0.42
0.30
0.38
0.26
0.30
0.30
0.32
0.32
0.27
0.25
0.25
0.22
0.15
0.14
0.06
0.21
0.23
0.23
0.25
0.29
0.36
0.17
0.00
0.12
-3
–0.07
0.36/
0.25/
0.44/
0.19/
0.07
0.20
0.31
0.67
0.35
0.39
0.44
0.47
0.34
0.43
0.29
0.34
0.33
0.36
0.36
0.30
0.28
0.28
0.24
0.17
0.16
0.07
0.24
0.25
0.26
0.29
0.33
0.40
0.18
0.00
0.14
Speed Grade
-2
–0.07
0.43/
0.32/
0.52/
0.24/
0.07
0.22
0.36
0.79
0.42
0.47
0.52
0.55
0.39
0.50
0.34
0.40
0.38
0.41
0.41
0.20
0.19
0.28
0.29
0.39
0.47
0.20
0.00
0.16
0.34
0.32
0.33
0.28
0.08
0.30
0.33
-1
–0.08
0.44/
0.32/
0.58/
0.23/
0.09
0.25
0.40
0.85
0.44
0.50
0.56
0.60
0.44
0.55
0.37
0.44
0.43
0.47
0.47
0.40
0.37
0.36
0.31
0.22
0.21
0.09
0.30
0.31
0.33
0.36
0.44
0.53
0.25
0.01
0.22
-1L
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
Units
37

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