XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 46

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Table 58: Configuration Switching Characteristics (Cont’d)
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
2.
3.
BPI Master Flash Mode Programming Switching
T
T
T
SPI Master Flash Mode Programming Switching
T
T
T
T
CCLK Output (Master Modes)
T
T
CCLK Input (Slave Modes)
T
T
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
F
T
T
T
T
T
T
T
BPICCO
BPIDCC
INITADDR
SPIDCC
SPICCM
SPICCFC
FSINIT
MCCKL
MCCKH
SCCKL
SCCKH
DCK
MMCMDCK_DADDR
MMCMCKD_DADDR
MMCMDCK_DI
MMCMDCK_DEN
MMCMDCK_DWE
MMCMCKO_DO
MMCMCKO_DRDY
To support longer delays in configuration, use the design solutions described in UG360:Virtex-6 FPGA Configuration User Guide.
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
DO will hold until next DRP operation.
/T
/T
/T
(2)
FSINITH
BPICCD
SPIDCCD
Symbol
/T
MMCMCKD_DI
/T
/T
MMCMCKD_DEN
MMCMCKD_DWE
/
ADDR[25:0], RS[1:0], FCS_B, FOE_B,
FWE_B outputs valid after CCLK rising
edge at 2.5V
ADDR[25:0], RS[1:0], FCS_B, FOE_B,
FWE_B outputs valid after CCLK rising
edge at 1.8V
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0]
address cycles
DIN Setup/Hold before/after the rising
CCLK edge
MOSI clock to out at 2.5V
MOSI clock to out at 1.8V
FCS_B clock to out at 2.5V
FCS_B clock to out at 1.8V
FS[2:0] to INIT_B rising edge Setup and
Hold
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
Maximum frequency for DCLK
DADDR Setup/Hold
DI Setup/Hold
DEN Setup/Hold time
DWE Setup/Hold time
CLK to out of DO
CLK to out of DRDY
Description
(3)
www.xilinx.com
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
4.0/0.0
3.0/0.0
45/55
45/55
1.25/
1.25/
1.25/
1.25/
0.00
0.00
0.00
0.00
2.60
0.32
200
2.5
2.5
-3
6
6
3
6
6
6
6
2
4.0/0.0
3.0/0.0
45/55
45/55
1.40/
1.40/
1.40/
1.40/
0.00
0.00
0.00
0.00
3.02
0.34
200
Speed Grade
2.5
2.5
-2
6
6
3
6
6
6
6
2
4.0/0.0
3.0/0.0
45/55
45/55
1.63/
1.63/
1.63/
1.63/
3.64
0.00
0.00
0.00
0.00
0.38
200
2.5
2.5
-1
6
6
3
6
6
6
6
2
5.0/0.0
3.5/0.0
40/60
40/60
1.64/
1.64/
1.64/
1.64/
0.00
0.00
0.00
0.00
3.68
0.38
200
-1L
2.5
2.5
7
7
3
7
7
7
7
2
CCLK cycles
%, Min/Max
%, Min/Max
ns, Min
ns, Min
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
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